Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11432346 [patent_doc_number] => 09570674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Magnetic device' [patent_app_type] => utility [patent_app_number] => 14/693852 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 10118 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693852
Magnetic device Apr 21, 2015 Issued
Array ( [id] => 12436983 [patent_doc_number] => 09978845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Method of obtaining planar semipolar gallium nitride surfaces [patent_app_type] => utility [patent_app_number] => 15/304189 [patent_app_country] => US [patent_app_date] => 2015-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 8979 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15304189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/304189
Method of obtaining planar semipolar gallium nitride surfaces Apr 14, 2015 Issued
Array ( [id] => 11517698 [patent_doc_number] => 20170084772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'CRYSTALLINE SILICON-BASED SOLAR CELL, CRYSTALLINE-SILICON SOLAR CELL MODULE, AND MANUFACTURING METHODS THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/308030 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8574 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15308030 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/308030
Crystalline silicon-based solar cell, crystalline-silicon solar cell module, and manufacturing methods therefor Apr 8, 2015 Issued
Array ( [id] => 10512927 [patent_doc_number] => 09240508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Thin film structures and devices with integrated light and heat blocking layers for laser patterning' [patent_app_type] => utility [patent_app_number] => 14/673151 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673151
Thin film structures and devices with integrated light and heat blocking layers for laser patterning Mar 29, 2015 Issued
Array ( [id] => 10525786 [patent_doc_number] => 09252308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Thin film structures and devices with integrated light and heat blocking layers for laser patterning' [patent_app_type] => utility [patent_app_number] => 14/673345 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673345
Thin film structures and devices with integrated light and heat blocking layers for laser patterning Mar 29, 2015 Issued
Array ( [id] => 10525798 [patent_doc_number] => 09252320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Thin film structures and devices with integrated light and heat blocking layers for laser patterning' [patent_app_type] => utility [patent_app_number] => 14/673249 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4654 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673249
Thin film structures and devices with integrated light and heat blocking layers for laser patterning Mar 29, 2015 Issued
Array ( [id] => 11300834 [patent_doc_number] => 09508846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process' [patent_app_type] => utility [patent_app_number] => 14/662652 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 6415 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/662652
Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process Mar 18, 2015 Issued
Array ( [id] => 10689642 [patent_doc_number] => 20160035788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/659806 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14659806 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/659806
Methods of manufacturing semiconductor devices Mar 16, 2015 Issued
Array ( [id] => 12346263 [patent_doc_number] => 09950922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Packaged microsystems [patent_app_type] => utility [patent_app_number] => 15/127237 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 10188 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15127237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/127237
Packaged microsystems Mar 16, 2015 Issued
Array ( [id] => 11071259 [patent_doc_number] => 20160268223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'METHODS FOR FORMING PILLAR BUMPS ON SEMICONDUCTOR WAFERS' [patent_app_type] => utility [patent_app_number] => 14/644473 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4839 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14644473 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/644473
Methods for forming pillar bumps on semiconductor wafers Mar 10, 2015 Issued
Array ( [id] => 11346453 [patent_doc_number] => 09530869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Methods of forming embedded source/drain regions on finFET devices' [patent_app_type] => utility [patent_app_number] => 14/643409 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4800 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14643409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/643409
Methods of forming embedded source/drain regions on finFET devices Mar 9, 2015 Issued
Array ( [id] => 10732969 [patent_doc_number] => 20160079119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/634705 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14634705 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/634705
Manufacturing method of semiconductor device Feb 26, 2015 Issued
Array ( [id] => 11483295 [patent_doc_number] => 09589849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Methods of modulating strain in PFET and NFET FinFET semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/633353 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 7362 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633353 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633353
Methods of modulating strain in PFET and NFET FinFET semiconductor devices Feb 26, 2015 Issued
Array ( [id] => 11057230 [patent_doc_number] => 20160254192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES' [patent_app_type] => utility [patent_app_number] => 14/633544 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633544 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633544
Methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devices Feb 26, 2015 Issued
Array ( [id] => 11539645 [patent_doc_number] => 09614063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Homoepitaxial tunnel barriers with functionalized graphene-on-graphene and methods of making' [patent_app_type] => utility [patent_app_number] => 14/629939 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4207 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629939
Homoepitaxial tunnel barriers with functionalized graphene-on-graphene and methods of making Feb 23, 2015 Issued
Array ( [id] => 11694308 [patent_doc_number] => 20170170025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SELECTIVE, ELECTROCHEMICAL ETCHING OF A SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 15/116041 [patent_app_country] => US [patent_app_date] => 2015-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15116041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/116041
Selective, electrochemical etching of a semiconductor Feb 9, 2015 Issued
Array ( [id] => 11710443 [patent_doc_number] => 20170178943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'ELECTROSTATIC HEATING SUBSTRATE HOLDER WHICH IS POLARISED AT HIGH VOLTAGE' [patent_app_type] => utility [patent_app_number] => 15/117024 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2389 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15117024 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/117024
Electrostatic heating substrate holder which is polarised at high voltage Feb 3, 2015 Issued
Array ( [id] => 11660043 [patent_doc_number] => 09673055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Method for quadruple frequency FinFETs with single-fin removal' [patent_app_type] => utility [patent_app_number] => 14/613416 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5912 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14613416 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/613416
Method for quadruple frequency FinFETs with single-fin removal Feb 3, 2015 Issued
Array ( [id] => 11411850 [patent_doc_number] => 09559166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Fabricating transistors having resurfaced source/drain regions with stressed portions' [patent_app_type] => utility [patent_app_number] => 14/609504 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5712 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/609504
Fabricating transistors having resurfaced source/drain regions with stressed portions Jan 29, 2015 Issued
Array ( [id] => 11028718 [patent_doc_number] => 20160225674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/608902 [patent_app_country] => US [patent_app_date] => 2015-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6489 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14608902 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/608902
Methods of forming NMOS and PMOS FinFET devices and the resulting product Jan 28, 2015 Issued
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