Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10230453 [patent_doc_number] => 20150115447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'INTERCONNECTS FOR SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/061782 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061782
Interconnects for semiconductor devices Oct 23, 2013 Issued
Array ( [id] => 10409852 [patent_doc_number] => 20150294861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'PRODUCTION METHOD FOR ACTIVE ELEMENT SUBSTRATE, ACTIVE ELEMENT SUBSTRATE, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/438141 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14438 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/438141
Production method for active element substrate, active element substrate, and display device Oct 20, 2013 Issued
Array ( [id] => 10399508 [patent_doc_number] => 20150284515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'SILICONE RESIN COMPOSITION, CURED SILICONE RESIN, AND SEALED OPTICAL SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/438499 [patent_app_country] => US [patent_app_date] => 2013-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7863 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/438499
Silicone resin composition, cured silicone resin, and sealed optical semiconductor element Oct 15, 2013 Issued
Array ( [id] => 10410134 [patent_doc_number] => 20150295143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL PAIRING WITH COMPOSITIONAL TRANSITION LAYER' [patent_app_type] => utility [patent_app_number] => 14/438213 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16653 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438213 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/438213
Semiconductor structure having nanocrystalline core and nanocrystalline shell paring with compositional transition layer Oct 10, 2013 Issued
Array ( [id] => 10898696 [patent_doc_number] => 08921917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Split gate flash cell and method for making the same' [patent_app_type] => utility [patent_app_number] => 14/038410 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038410 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038410
Split gate flash cell and method for making the same Sep 25, 2013 Issued
Array ( [id] => 9266609 [patent_doc_number] => 20140021525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 14/033886 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 114 [patent_no_of_words] => 10416 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033886 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/033886
Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method for manufacturing nonvolatile semiconductor memory Sep 22, 2013 Issued
Array ( [id] => 9202346 [patent_doc_number] => 20140001522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/964575 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7390 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964575 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964575
Method for manufacturing solid-state imaging device Aug 11, 2013 Issued
Array ( [id] => 9158813 [patent_doc_number] => 20130307090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THE THRESHOLD ADJUSTMENT' [patent_app_type] => utility [patent_app_number] => 13/948672 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8581 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948672 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/948672
ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THE THRESHOLD ADJUSTMENT Jul 22, 2013 Abandoned
Array ( [id] => 9104601 [patent_doc_number] => 20130277732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 13/919655 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3668 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919655 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/919655
Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same Jun 16, 2013 Issued
Array ( [id] => 9065017 [patent_doc_number] => 20130256773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'ELECTRICALLY ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/899369 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3583 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13899369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/899369
Electrically erasable programmable non-volatile memory May 20, 2013 Issued
Array ( [id] => 10929838 [patent_doc_number] => 20140332859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'Self-Aligned Wrapped-Around Structure' [patent_app_type] => utility [patent_app_number] => 13/782528 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13782528 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/782528
Self-aligned wrapped-around structure May 9, 2013 Issued
Array ( [id] => 9135019 [patent_doc_number] => 20130295734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD FOR FORMING GATE, SOURCE, AND DRAIN CONTACTS ON A MOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/871884 [patent_app_country] => US [patent_app_date] => 2013-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5110 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13871884 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/871884
Method for forming gate, source, and drain contacts on a MOS transistor Apr 25, 2013 Issued
Array ( [id] => 9662946 [patent_doc_number] => 08809931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/847765 [patent_app_country] => US [patent_app_date] => 2013-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 49 [patent_no_of_words] => 18365 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13847765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/847765
Nonvolatile semiconductor memory device Mar 19, 2013 Issued
Array ( [id] => 9065073 [patent_doc_number] => 20130256829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/845033 [patent_app_country] => US [patent_app_date] => 2013-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9396 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845033 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845033
Compound semiconductor device and method of manufacturing the same Mar 16, 2013 Issued
Array ( [id] => 9728824 [patent_doc_number] => 20140264531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/834667 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 25127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834667
NONVOLATILE SEMICONDUCTOR MEMORY Mar 14, 2013 Abandoned
Array ( [id] => 9728825 [patent_doc_number] => 20140264532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY' [patent_app_type] => utility [patent_app_number] => 13/838297 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10399 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838297
Floating gate memory cells in vertical memory Mar 14, 2013 Issued
Array ( [id] => 9051264 [patent_doc_number] => 20130248978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/837246 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10286 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837246 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/837246
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Mar 14, 2013 Abandoned
Array ( [id] => 9728820 [patent_doc_number] => 20140264527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'LOCAL BURIED CHANNEL DIELECTRIC FOR VERTICAL NAND PERFORMANCE ENHANCEMENT AND VERTICAL SCALING' [patent_app_type] => utility [patent_app_number] => 13/832721 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832721
Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling Mar 14, 2013 Issued
Array ( [id] => 8973772 [patent_doc_number] => 20130207202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'MEMORY CELL ARRAY WITH SEMICONDUCTOR SELECTION DEVICE FOR MULTIPLE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/835552 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3326 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835552
Memory cell array with semiconductor selection device for multiple memory cells Mar 14, 2013 Issued
Array ( [id] => 9728834 [patent_doc_number] => 20140264541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Structure and Method for Manufacture of Memory Device With Thin Silicon Body' [patent_app_type] => utility [patent_app_number] => 13/829392 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6670 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13829392 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/829392
Structure and method for manufacture of memory device with thin silicon body Mar 13, 2013 Issued
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