Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10858124 [patent_doc_number] => 08884329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Semiconductor light-emitting element, electrode structure and light-emitting device' [patent_app_type] => utility [patent_app_number] => 13/451192 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 18328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451192
Semiconductor light-emitting element, electrode structure and light-emitting device Apr 18, 2012 Issued
Array ( [id] => 9104697 [patent_doc_number] => 20130277828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Methods and Apparatus for bump-on-trace Chip Packaging' [patent_app_type] => utility [patent_app_number] => 13/450191 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2886 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450191
Methods and Apparatus for bump-on-trace Chip Packaging Apr 17, 2012 Abandoned
Array ( [id] => 8582710 [patent_doc_number] => 20130001531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'ORGANIC LIGHT-EMITTING DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/450363 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8169 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450363 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450363
Organic light-emitting display apparatus Apr 17, 2012 Issued
Array ( [id] => 9104587 [patent_doc_number] => 20130277718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'JFET DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/450373 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4008 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450373 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450373
JFET device and method of manufacturing the same Apr 17, 2012 Issued
Array ( [id] => 9575969 [patent_doc_number] => 08766386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Solid-state imaging device' [patent_app_type] => utility [patent_app_number] => 13/449374 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5417 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449374
Solid-state imaging device Apr 17, 2012 Issued
Array ( [id] => 8462623 [patent_doc_number] => 20120267791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'MULTI CHIP PACKAGE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE MULTI CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/450164 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4446 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450164
Multi chip package, manufacturing method thereof, and memory system having the multi chip package Apr 17, 2012 Issued
Array ( [id] => 9350749 [patent_doc_number] => 08669643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Wiring board, semiconductor device, and method for manufacturing wiring board' [patent_app_type] => utility [patent_app_number] => 13/448992 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 39 [patent_no_of_words] => 9914 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/448992
Wiring board, semiconductor device, and method for manufacturing wiring board Apr 16, 2012 Issued
Array ( [id] => 10099883 [patent_doc_number] => 09136202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Enhanced package thermal management using external and internal capacitive thermal material' [patent_app_type] => utility [patent_app_number] => 13/448711 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4791 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448711 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/448711
Enhanced package thermal management using external and internal capacitive thermal material Apr 16, 2012 Issued
Array ( [id] => 9889414 [patent_doc_number] => 08975673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Method of trimming spacers and semiconductor structure thereof' [patent_app_type] => utility [patent_app_number] => 13/447311 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3178 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447311 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/447311
Method of trimming spacers and semiconductor structure thereof Apr 15, 2012 Issued
Array ( [id] => 8335626 [patent_doc_number] => 20120202329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/448046 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3820 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/448046
Charge trap type non-volatile memory device and method for fabricating the same Apr 15, 2012 Issued
Array ( [id] => 8450838 [patent_doc_number] => 20120261783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'BACK-SIDE ILLUMINATED IMAGE SENSOR PROVIDED WITH A TRANSPARENT ELECTRODE' [patent_app_type] => utility [patent_app_number] => 13/445222 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2818 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445222
Back-side illuminated image sensor provided with a transparent electrode Apr 11, 2012 Issued
Array ( [id] => 9762106 [patent_doc_number] => 08846426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Organic EL device and manufacturing method thereof, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/445322 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 23270 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445322 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445322
Organic EL device and manufacturing method thereof, and electronic apparatus Apr 11, 2012 Issued
Array ( [id] => 8486893 [patent_doc_number] => 20120286300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'DISPLAY DEVICE, DISPLAY, AND ELECTRONIC UNIT' [patent_app_type] => utility [patent_app_number] => 13/445652 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13885 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445652 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445652
Display device, display, and electronic unit Apr 11, 2012 Issued
Array ( [id] => 8475401 [patent_doc_number] => 20120274807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/442310 [patent_app_country] => US [patent_app_date] => 2012-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14610 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/442310
Method of manufacturing organic electroluminescence display device Apr 8, 2012 Issued
Array ( [id] => 8299065 [patent_doc_number] => 20120181631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING' [patent_app_type] => utility [patent_app_number] => 13/431328 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5840 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431328
Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering Mar 26, 2012 Issued
Array ( [id] => 8310429 [patent_doc_number] => 20120187453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS' [patent_app_type] => utility [patent_app_number] => 13/431537 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431537
INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS Mar 26, 2012 Abandoned
Array ( [id] => 8913974 [patent_doc_number] => 20130175599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'INLINE METHOD TO MONITOR ONO STACK QUALITY' [patent_app_type] => utility [patent_app_number] => 13/430631 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430631 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430631
Inline method to monitor ONO stack quality Mar 25, 2012 Issued
Array ( [id] => 9216222 [patent_doc_number] => 08629022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 13/420730 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420730
Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same Mar 14, 2012 Issued
Array ( [id] => 8960313 [patent_doc_number] => 20130199915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'Connecting Conductive Layers Using In-Mould Lamination And Decoration' [patent_app_type] => utility [patent_app_number] => 13/367958 [patent_app_country] => US [patent_app_date] => 2012-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13367958 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/367958
Connecting conductive layers using in-mould lamination and decoration Feb 6, 2012 Issued
Array ( [id] => 8166086 [patent_doc_number] => 20120104416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'BIPOLAR JUNCTION TRANSISTOR GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF' [patent_app_type] => utility [patent_app_number] => 13/344234 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4933 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104416.pdf [firstpage_image] =>[orig_patent_app_number] => 13344234 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344234
Bipolar junction transistor guard ring structures and method of fabricating thereof Jan 4, 2012 Issued
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