Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10898704 [patent_doc_number] => 08921925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Semiconductor device, method of manufacturing the same, and power module' [patent_app_type] => utility [patent_app_number] => 13/339072 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10881 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339072 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339072
Semiconductor device, method of manufacturing the same, and power module Dec 27, 2011 Issued
Array ( [id] => 8127577 [patent_doc_number] => 20120088335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'MANUFACTURING METHOD OF THE ELECTRONIC COMPONENT' [patent_app_type] => utility [patent_app_number] => 13/313908 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7427 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20120088335.pdf [firstpage_image] =>[orig_patent_app_number] => 13313908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313908
Manufacturing method of the electronic component Dec 6, 2011 Issued
Array ( [id] => 9413536 [patent_doc_number] => 08697573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Process to remove Ni and Pt residues for NiPtSi applications using aqua regia with microwave assisted heating' [patent_app_type] => utility [patent_app_number] => 13/292906 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8061 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/292906
Process to remove Ni and Pt residues for NiPtSi applications using aqua regia with microwave assisted heating Nov 8, 2011 Issued
Array ( [id] => 8421696 [patent_doc_number] => 08278184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-02 [patent_title] => 'Fabrication method of a non-planar transistor' [patent_app_type] => utility [patent_app_number] => 13/287131 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2133 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/287131
Fabrication method of a non-planar transistor Nov 1, 2011 Issued
Array ( [id] => 8987102 [patent_doc_number] => 20130214383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'METHOD FOR FORMING ISOLATION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/881560 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13881560 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/881560
Method for forming isolation structure Nov 1, 2011 Issued
Array ( [id] => 8920877 [patent_doc_number] => 08486810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Method for fabricating a substrate provided with two active areas with different semiconductor materials' [patent_app_type] => utility [patent_app_number] => 13/280694 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4237 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280694 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280694
Method for fabricating a substrate provided with two active areas with different semiconductor materials Oct 24, 2011 Issued
Array ( [id] => 9537756 [patent_doc_number] => 20140162404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'METHOD FOR PACKAGING LOW-K CHIP' [patent_app_type] => utility [patent_app_number] => 14/233461 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2493 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14233461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/233461
Method for packaging low-K chip Oct 20, 2011 Issued
Array ( [id] => 7767227 [patent_doc_number] => 20120034748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'METHOD OF FABRICATING TRANSISTOR FOR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/277751 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2460 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034748.pdf [firstpage_image] =>[orig_patent_app_number] => 13277751 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/277751
Method of fabricating transistor for semiconductor device Oct 19, 2011 Issued
Array ( [id] => 8777338 [patent_doc_number] => 20130099313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/276395 [patent_app_country] => US [patent_app_date] => 2011-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276395 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/276395
FinFET structure and method to adjust threshold voltage in a FinFET structure Oct 18, 2011 Issued
Array ( [id] => 8159395 [patent_doc_number] => 20120100678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'METHOD FOR FORMING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/271874 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 21771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20120100678.pdf [firstpage_image] =>[orig_patent_app_number] => 13271874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271874
Method for forming semiconductor device Oct 11, 2011 Issued
Array ( [id] => 9777830 [patent_doc_number] => 08853035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Tucked active region without dummy poly for performance boost and variation reduction' [patent_app_type] => utility [patent_app_number] => 13/253375 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 8090 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253375
Tucked active region without dummy poly for performance boost and variation reduction Oct 4, 2011 Issued
Array ( [id] => 8742592 [patent_doc_number] => 20130082309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/252346 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252346 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/252346
Semiconductor device and fabrication method thereof Oct 3, 2011 Issued
Array ( [id] => 8744965 [patent_doc_number] => 20130084682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/248319 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248319 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248319
Semiconductor device and fabrication method thereof Sep 28, 2011 Issued
Array ( [id] => 8713183 [patent_doc_number] => 08399323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method for fabricating vertical channel type nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/244247 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3518 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244247 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/244247
Method for fabricating vertical channel type nonvolatile memory device Sep 22, 2011 Issued
Array ( [id] => 8720764 [patent_doc_number] => 20130071981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'FABRICATING METHOD OF SEMICONDUCTOR ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/238045 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1483 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238045
Fabricating method of semiconductor elements Sep 20, 2011 Issued
Array ( [id] => 8417172 [patent_doc_number] => 20120244673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/236716 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6661 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236716
Method for manufacturing semiconductor device Sep 19, 2011 Issued
Array ( [id] => 8720761 [patent_doc_number] => 20130071978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'FABRICATING METHOD OF TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/236656 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2555 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236656 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236656
Fabricating method of transistor Sep 19, 2011 Issued
Array ( [id] => 8720760 [patent_doc_number] => 20130071977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 13/237688 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237688
Methods for fabricating integrated circuits having gate to active and gate to gate interconnects Sep 19, 2011 Issued
Array ( [id] => 8249026 [patent_doc_number] => 20120153354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP' [patent_app_type] => utility [patent_app_number] => 13/236226 [patent_app_country] => US [patent_app_date] => 2011-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153354.pdf [firstpage_image] =>[orig_patent_app_number] => 13236226 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236226
PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP Sep 18, 2011 Abandoned
Array ( [id] => 8329118 [patent_doc_number] => 08237218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Nonvolatile semiconductor memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/226224 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 6727 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13226224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/226224
Nonvolatile semiconductor memory device and method of manufacturing the same Sep 5, 2011 Issued
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