Errol V. Fernandes

Array ( [id] => 19444534 [patent_doc_number] => 12094825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Interconnection between chips by bridge chip [patent_app_type] => utility [patent_app_number] => 18/344418 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 36 [patent_no_of_words] => 11635 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18743483 [patent_doc_number] => 20230352471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INTEGRATED CIRCUIT PACKAGES [patent_app_type] => utility [patent_app_number] => 18/344456 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18833896 [patent_doc_number] => 20230402423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR PACKAGE HAVING AT LEAST ONE ELECTRICALLY CONDUCTIVE SPACER AND METHOD OF FORMING THE SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/336067 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20793086 [patent_doc_number] => 12667020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Hybrid underfill structures for multi-die packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/335302 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 7522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18906110 [patent_doc_number] => 20240021595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/209500 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20484264 [patent_doc_number] => 12532745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Electronic package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/334434 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19634672 [patent_doc_number] => 20240413121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/332761 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19260966 [patent_doc_number] => 12021032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Semiconductor package having an interposer and method of manufacturing semiconductor package [patent_app_type] => utility [patent_app_number] => 18/326325 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 8632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18661407 [patent_doc_number] => 20230307421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => PACKAGE-ON-PACKAGE HAVING A THICK LOGIC DIE [patent_app_type] => utility [patent_app_number] => 18/203631 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20649817 [patent_doc_number] => 12604781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Package structure including guiding patterns [patent_app_type] => utility [patent_app_number] => 18/324989 [patent_app_country] => US [patent_app_date] => 2023-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 1982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20469543 [patent_doc_number] => 12525586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/202375 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 1037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19604882 [patent_doc_number] => 20240395762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/201319 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20532343 [patent_doc_number] => 12550798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Interposer with built-in wiring for testing an embedded integrated passive device and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/322735 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19199097 [patent_doc_number] => 11996346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/321739 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 11996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18633511 [patent_doc_number] => 20230292438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => RADIO FREQUENCY FRONT-END MODULE, MANUFACTURING METHOD THEREOF AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/200230 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19199217 [patent_doc_number] => 11996467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Method for epitaxial growth and device [patent_app_type] => utility [patent_app_number] => 18/317319 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 53 [patent_no_of_words] => 10457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18743481 [patent_doc_number] => 20230352469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => STACKED MEMORY POP STRUCTURE AND PACKAGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/139777 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19964844 [patent_doc_number] => 12334361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Substrate structure, and fabrication and packaging methods thereof [patent_app_type] => utility [patent_app_number] => 18/139141 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 3510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19231272 [patent_doc_number] => 12010926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Magnetic tunnel junction (MTJ) device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/138137 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3594 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18555340 [patent_doc_number] => 20230253357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => Honeycomb Pattern for Conductive Features [patent_app_type] => utility [patent_app_number] => 18/300862 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300862 [rel_patent_id] =>[rel_patent_doc_number] =>)