
Errol V. Fernandes
Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2821, 2893 |
| Total Applications | 1197 |
| Issued Applications | 1012 |
| Pending Applications | 72 |
| Abandoned Applications | 130 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19712821
[patent_doc_number] => 20250022963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => THIN FILM TRANSISTOR HAVING SPINEL SINGLE-PHASE CRYSTALLINE IZTO OXIDE SEMICONDUCTOR
[patent_app_type] => utility
[patent_app_number] => 18/712710
[patent_app_country] => US
[patent_app_date] => 2022-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5889
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18712710
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/712710 | THIN FILM TRANSISTOR HAVING SPINEL SINGLE-PHASE CRYSTALLINE IZTO OXIDE SEMICONDUCTOR | Dec 5, 2022 | Pending |
Array
(
[id] => 18857218
[patent_doc_number] => 11854809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Manufacturing method of a semiconductor device with efficient edge structure
[patent_app_type] => utility
[patent_app_number] => 18/061795
[patent_app_country] => US
[patent_app_date] => 2022-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4933
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061795
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/061795 | Manufacturing method of a semiconductor device with efficient edge structure | Dec 4, 2022 | Issued |
Array
(
[id] => 19221584
[patent_doc_number] => 20240186288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/060573
[patent_app_country] => US
[patent_app_date] => 2022-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7293
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060573
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/060573 | Semiconductor package and manufacturing method thereof | Nov 30, 2022 | Issued |
Array
(
[id] => 19206202
[patent_doc_number] => 20240178101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA
[patent_app_type] => utility
[patent_app_number] => 18/072569
[patent_app_country] => US
[patent_app_date] => 2022-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16712
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072569
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/072569 | INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA | Nov 29, 2022 | Pending |
Array
(
[id] => 18243424
[patent_doc_number] => 20230075735
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/985166
[patent_app_country] => US
[patent_app_date] => 2022-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12559
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985166
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/985166 | Package structure and method of manufacturing the same | Nov 10, 2022 | Issued |
Array
(
[id] => 18424005
[patent_doc_number] => 20230178469
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-08
[patent_title] => SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER
[patent_app_type] => utility
[patent_app_number] => 18/054225
[patent_app_country] => US
[patent_app_date] => 2022-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15196
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054225
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/054225 | SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER | Nov 9, 2022 | Pending |
Array
(
[id] => 18500556
[patent_doc_number] => 20230223350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-13
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/981535
[patent_app_country] => US
[patent_app_date] => 2022-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981535
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/981535 | Semiconductor package and method of fabricating the same | Nov 6, 2022 | Issued |
Array
(
[id] => 19146389
[patent_doc_number] => 20240145419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => LASING TO ATTACH DIE TO LEAD FRAME
[patent_app_type] => utility
[patent_app_number] => 17/977610
[patent_app_country] => US
[patent_app_date] => 2022-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3795
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977610
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/977610 | LASING TO ATTACH DIE TO LEAD FRAME | Oct 30, 2022 | Pending |
Array
(
[id] => 20305414
[patent_doc_number] => 12451414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Semiconductor package
[patent_app_type] => utility
[patent_app_number] => 18/050705
[patent_app_country] => US
[patent_app_date] => 2022-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 4541
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050705
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/050705 | Semiconductor package | Oct 27, 2022 | Issued |
Array
(
[id] => 18394840
[patent_doc_number] => 20230163061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/975692
[patent_app_country] => US
[patent_app_date] => 2022-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2296
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 358
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975692
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/975692 | Semiconductor package | Oct 27, 2022 | Issued |
Array
(
[id] => 20118395
[patent_doc_number] => 12368113
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Methods and apparatus for using spacer-on-spacer design for solder joint reliability improvement in semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/976409
[patent_app_country] => US
[patent_app_date] => 2022-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 1047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976409
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/976409 | Methods and apparatus for using spacer-on-spacer design for solder joint reliability improvement in semiconductor devices | Oct 27, 2022 | Issued |
Array
(
[id] => 19007948
[patent_doc_number] => 20240072019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/975455
[patent_app_country] => US
[patent_app_date] => 2022-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4607
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975455
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/975455 | Electronic package and manufacturing method thereof | Oct 26, 2022 | Issued |
Array
(
[id] => 20389346
[patent_doc_number] => 12489081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Semiconductor package including underfill and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/049428
[patent_app_country] => US
[patent_app_date] => 2022-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 30
[patent_no_of_words] => 2122
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049428
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/049428 | Semiconductor package including underfill and method of forming the same | Oct 24, 2022 | Issued |
Array
(
[id] => 19038297
[patent_doc_number] => 20240088112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => Dual Die Integrated Circuit System in an Integrated Circuit Package with two Separate Supply Domains
[patent_app_type] => utility
[patent_app_number] => 17/955760
[patent_app_country] => US
[patent_app_date] => 2022-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955760
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/955760 | Dual die integrated circuit system in an integrated circuit package with two separate supply domains | Sep 28, 2022 | Issued |
Array
(
[id] => 18500522
[patent_doc_number] => 20230223316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-13
[patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/956566
[patent_app_country] => US
[patent_app_date] => 2022-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956566
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/956566 | Electronic package and manufacturing method thereof | Sep 28, 2022 | Issued |
Array
(
[id] => 18891092
[patent_doc_number] => 11869870
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-01-09
[patent_title] => Bonding process with inhibited oxide formation
[patent_app_type] => utility
[patent_app_number] => 17/953697
[patent_app_country] => US
[patent_app_date] => 2022-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 1924
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953697
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/953697 | Bonding process with inhibited oxide formation | Sep 26, 2022 | Issued |
Array
(
[id] => 20776993
[patent_doc_number] => 12660692
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-16
[patent_title] => Semiconductor package assembly and manufacturing method
[patent_app_type] => utility
[patent_app_number] => 17/952404
[patent_app_country] => US
[patent_app_date] => 2022-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 3280
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952404
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/952404 | Semiconductor package assembly and manufacturing method | Sep 25, 2022 | Issued |
Array
(
[id] => 18608187
[patent_doc_number] => 11749665
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-05
[patent_title] => Face-to-face semiconductor device with fan-out porch
[patent_app_type] => utility
[patent_app_number] => 17/952563
[patent_app_country] => US
[patent_app_date] => 2022-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5016
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952563
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/952563 | Face-to-face semiconductor device with fan-out porch | Sep 25, 2022 | Issued |
Array
(
[id] => 18140992
[patent_doc_number] => 20230014834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/935068
[patent_app_country] => US
[patent_app_date] => 2022-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7944
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935068
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/935068 | Semiconductor package | Sep 22, 2022 | Issued |
Array
(
[id] => 18473232
[patent_doc_number] => 20230207520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/934135
[patent_app_country] => US
[patent_app_date] => 2022-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7034
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934135
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/934135 | Semiconductor device | Sep 20, 2022 | Issued |