Search

Errol V. Fernandes

Examiner (ID: 18752, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2893, 2894, 2821
Total Applications
1201
Issued Applications
1015
Pending Applications
73
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18751473 [patent_doc_number] => 11810793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Semiconductor packages and methods of forming same [patent_app_type] => utility [patent_app_number] => 17/873640 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873640 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873640
Semiconductor packages and methods of forming same Jul 25, 2022 Issued
Array ( [id] => 18751509 [patent_doc_number] => 11810830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Chip package structure with cavity in interposer [patent_app_type] => utility [patent_app_number] => 17/814874 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814874
Chip package structure with cavity in interposer Jul 25, 2022 Issued
Array ( [id] => 17993292 [patent_doc_number] => 20220359329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Integrated Circuit Package and Method of Forming Same [patent_app_type] => utility [patent_app_number] => 17/872488 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872488
Integrated circuit package and method of forming same Jul 24, 2022 Issued
Array ( [id] => 17986070 [patent_doc_number] => 20220352107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/863818 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863818
Semiconductor package Jul 12, 2022 Issued
Array ( [id] => 19964931 [patent_doc_number] => 12334451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Semiconductor package including package substrate with dummy via and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/862040 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 5430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862040
Semiconductor package including package substrate with dummy via and method of forming the same Jul 10, 2022 Issued
Array ( [id] => 19918600 [patent_doc_number] => 12293976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Semiconductor EMI shielding component, semiconductor package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/858286 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858286 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858286
Semiconductor EMI shielding component, semiconductor package structure and manufacturing method thereof Jul 5, 2022 Issued
Array ( [id] => 18891043 [patent_doc_number] => 11869820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => IC having a metal ring thereon for stress reduction [patent_app_type] => utility [patent_app_number] => 17/810568 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 4078 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810568
IC having a metal ring thereon for stress reduction Jun 30, 2022 Issued
Array ( [id] => 18882997 [patent_doc_number] => 20240006366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THROUGH DIELECTRIC VIA [patent_app_type] => utility [patent_app_number] => 17/854613 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854613 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854613
Microelectronic assemblies including stacked dies coupled by a through dielectric via Jun 29, 2022 Issued
Array ( [id] => 19468399 [patent_doc_number] => 20240322069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => OPTOELECTRONIC SEMICONDUCTOR DEVICE, ARRAY OF OPTOELECTRONIC SEMICONDUCTOR DEVICES AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/572699 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18572699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/572699
OPTOELECTRONIC SEMICONDUCTOR DEVICE, ARRAY OF OPTOELECTRONIC SEMICONDUCTOR DEVICES AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE Jun 28, 2022 Pending
Array ( [id] => 20869882 [patent_doc_number] => 12696801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Package architecture with compute bricks having vertically stacked dies [patent_app_type] => utility [patent_app_number] => 17/852992 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 22346 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852992
PACKAGE ARCHITECTURE WITH COMPUTE BRICKS HAVING VERTICALLY STACKED DIES Jun 28, 2022 Pending
Array ( [id] => 19467920 [patent_doc_number] => 20240321590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD [patent_app_type] => utility [patent_app_number] => 18/572938 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18572938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/572938
SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD Jun 21, 2022 Pending
Array ( [id] => 17917945 [patent_doc_number] => 20220320341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/844745 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844745
Method for manufacturing non-volatile memory device Jun 20, 2022 Issued
Array ( [id] => 20776873 [patent_doc_number] => 12660571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Method for forming thermal oxide film on semiconductor substrate and method for producing semiconductor device [patent_app_type] => utility [patent_app_number] => 18/566907 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2487 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18566907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/566907
Method for forming thermal oxide film on semiconductor substrate and method for producing semiconductor device Jun 5, 2022 Issued
Array ( [id] => 20376939 [patent_doc_number] => 12484397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Display apparatus [patent_app_type] => utility [patent_app_number] => 17/831492 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831492
Display apparatus Jun 2, 2022 Issued
Array ( [id] => 20307142 [patent_doc_number] => 12453153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Work-function layers in the gates of pFETs [patent_app_type] => utility [patent_app_number] => 17/804971 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 46 [patent_no_of_words] => 3186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804971
Work-function layers in the gates of pFETs May 31, 2022 Issued
Array ( [id] => 20161402 [patent_doc_number] => 12388038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Semiconductor packages including mixed bond types and methods of forming same [patent_app_type] => utility [patent_app_number] => 17/825042 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825042
Semiconductor packages including mixed bond types and methods of forming same May 25, 2022 Issued
Array ( [id] => 20259051 [patent_doc_number] => 12431415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Buffer block structures for C4 bonding and methods of using the same [patent_app_type] => utility [patent_app_number] => 17/730410 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 7932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730410
Buffer block structures for C4 bonding and methods of using the same Apr 26, 2022 Issued
Array ( [id] => 20404455 [patent_doc_number] => 12494436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Integrated passive device dies and methods of forming and placement of the same [patent_app_type] => utility [patent_app_number] => 17/723954 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723954
Integrated passive device dies and methods of forming and placement of the same Apr 18, 2022 Issued
Array ( [id] => 17764868 [patent_doc_number] => 20220238481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => CHIP ASSEMBLING ON ADHESION LAYER OR DIELECTRIC LAYER, EXTENDING BEYOND CHIP, ON SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/722929 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722929
Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate Apr 17, 2022 Issued
Array ( [id] => 17833703 [patent_doc_number] => 20220271007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/723386 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723386
Overlapping die stacks for nand package architecture Apr 17, 2022 Issued
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