Search

Esaw T. Abraham

Examiner (ID: 18736, Phone: (571)272-3812 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2133, 2112, 2784
Total Applications
1849
Issued Applications
1647
Pending Applications
120
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18249500 [patent_doc_number] => 11606105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Dynamic multi-stage decoding [patent_app_type] => utility [patent_app_number] => 17/529193 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529193
Dynamic multi-stage decoding Nov 16, 2021 Issued
Array ( [id] => 18304972 [patent_doc_number] => 11626889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-11 [patent_title] => Partial update sharing in joint LDPC decoding and ancillary processors [patent_app_type] => utility [patent_app_number] => 17/527683 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527683
Partial update sharing in joint LDPC decoding and ancillary processors Nov 15, 2021 Issued
Array ( [id] => 17535466 [patent_doc_number] => 20220114075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => LIVENESS AS A FACTOR TO EVALUATE MEMORY VULNERABILITY TO SOFT ERRORS [patent_app_type] => utility [patent_app_number] => 17/522417 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522417
Liveness as a factor to evaluate memory vulnerability to soft errors Nov 8, 2021 Issued
Array ( [id] => 18842083 [patent_doc_number] => 20230404487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHOD OF FORMING MODIFYING DATA RELATED TO DATA SEQUENCE OF DATA FRAME INCLUDING ELECTROENCEPHALOGRAM DATA, PROCESSING METHOD OF ELECTROENCEPHALOGRAM DATA AND ELECTROENCEPHALOGRAM APPARATUS [patent_app_type] => utility [patent_app_number] => 18/252505 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18252505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/252505
METHOD OF FORMING MODIFYING DATA RELATED TO DATA SEQUENCE OF DATA FRAME INCLUDING ELECTROENCEPHALOGRAM DATA, PROCESSING METHOD OF ELECTROENCEPHALOGRAM DATA AND ELECTROENCEPHALOGRAM APPARATUS Nov 8, 2021 Pending
Array ( [id] => 17417805 [patent_doc_number] => 20220052709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => CRC INTERLEAVING PATTERN FOR POLAR CODES [patent_app_type] => utility [patent_app_number] => 17/514249 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/514249
CRC interleaving pattern for polar codes Oct 28, 2021 Issued
Array ( [id] => 18688914 [patent_doc_number] => 11784664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Methods and systems for bit error determination and correction [patent_app_type] => utility [patent_app_number] => 17/502583 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 19900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502583
Methods and systems for bit error determination and correction Oct 14, 2021 Issued
Array ( [id] => 18079554 [patent_doc_number] => 20220405166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR SYSTEM RELATED TO PERFORMING AN ERROR CORRECTION OPERATION USING AN ERROR CORRECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/494468 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494468
Semiconductor system related to performing an error correction operation using an error correction method Oct 4, 2021 Issued
Array ( [id] => 19314208 [patent_doc_number] => 12040032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Electronic circuit and method for self-diagnosis of a data memory [patent_app_type] => utility [patent_app_number] => 18/018211 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8476 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18018211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/018211
Electronic circuit and method for self-diagnosis of a data memory Sep 28, 2021 Issued
Array ( [id] => 18277561 [patent_doc_number] => 11616515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Method and apparatus for fast decoding linear code based on soft decision [patent_app_type] => utility [patent_app_number] => 17/479612 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479612
Method and apparatus for fast decoding linear code based on soft decision Sep 19, 2021 Issued
Array ( [id] => 18249564 [patent_doc_number] => 11606169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Systems and methods for prioritizing packet retransmission [patent_app_type] => utility [patent_app_number] => 17/466373 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466373
Systems and methods for prioritizing packet retransmission Sep 2, 2021 Issued
Array ( [id] => 17293532 [patent_doc_number] => 20210389371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => DEBUG DATA COMMUNICATION SYSTEM FOR MULTIPLE CHIPS [patent_app_type] => utility [patent_app_number] => 17/461364 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461364
Debug data communication system for multiple chips Aug 29, 2021 Issued
Array ( [id] => 17296034 [patent_doc_number] => 20210391873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => NEURAL NETWORK-BASED QUANTUM ERROR CORRECTION DECODING METHOD AND APPARATUS, AND CHIP [patent_app_type] => utility [patent_app_number] => 17/460011 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460011
Neural network-based quantum error correction decoding method and apparatus, and chip Aug 26, 2021 Issued
Array ( [id] => 18463117 [patent_doc_number] => 11687407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Shared error correction code (ECC) circuitry [patent_app_type] => utility [patent_app_number] => 17/412050 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13831 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412050
Shared error correction code (ECC) circuitry Aug 24, 2021 Issued
Array ( [id] => 18797490 [patent_doc_number] => 11831336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Quantum computing error correction method, code, and system [patent_app_type] => utility [patent_app_number] => 17/444943 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 22207 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17444943 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/444943
Quantum computing error correction method, code, and system Aug 11, 2021 Issued
Array ( [id] => 18386156 [patent_doc_number] => 11656937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Techniques for error detection and correction in a memory system [patent_app_type] => utility [patent_app_number] => 17/396522 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396522
Techniques for error detection and correction in a memory system Aug 5, 2021 Issued
Array ( [id] => 17758532 [patent_doc_number] => 11398835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Managing defective bitline locations in a bit flipping decoder [patent_app_type] => utility [patent_app_number] => 17/395024 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395024
Managing defective bitline locations in a bit flipping decoder Aug 4, 2021 Issued
Array ( [id] => 17233149 [patent_doc_number] => 20210359706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => METHODS AND APPARATUS FOR CONSTRUCTING POLAR CODES [patent_app_type] => utility [patent_app_number] => 17/443992 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443992
Methods and apparatus for constructing polar codes Jul 28, 2021 Issued
Array ( [id] => 17233149 [patent_doc_number] => 20210359706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => METHODS AND APPARATUS FOR CONSTRUCTING POLAR CODES [patent_app_type] => utility [patent_app_number] => 17/443992 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443992
Methods and apparatus for constructing polar codes Jul 28, 2021 Issued
Array ( [id] => 17615118 [patent_doc_number] => 20220157398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => System and Method for Error Correction [patent_app_type] => utility [patent_app_number] => 17/443061 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443061
System and method for error correction Jul 19, 2021 Issued
Array ( [id] => 17347977 [patent_doc_number] => 20220014308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => Re-Transmission CRC For Polar Coding Incremental-Redundancy HARQ [patent_app_type] => utility [patent_app_number] => 17/368575 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368575
Re-transmission CRC for polar coding incremental-redundancy HARQ Jul 5, 2021 Issued
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