Search

Esaw T. Abraham

Examiner (ID: 18736, Phone: (571)272-3812 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2133, 2112, 2784
Total Applications
1849
Issued Applications
1647
Pending Applications
120
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17339211 [patent_doc_number] => 20220005542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/368018 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368018
Buffer circuit with adaptive repair capability Jul 5, 2021 Issued
Array ( [id] => 19705590 [patent_doc_number] => 12199640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Method and apparatus for receiving PPDU in which data is duplicated in wireless LAN system [patent_app_type] => utility [patent_app_number] => 18/010979 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 22172 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18010979 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/010979
Method and apparatus for receiving PPDU in which data is duplicated in wireless LAN system Jun 29, 2021 Issued
Array ( [id] => 17175046 [patent_doc_number] => 20210328717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => Audio data recovery method, device and Bluetooth Apparatus Device [patent_app_type] => utility [patent_app_number] => 17/359606 [patent_app_country] => US [patent_app_date] => 2021-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359606
Audio data recovery method, device and Bluetooth Apparatus Device Jun 26, 2021 Abandoned
Array ( [id] => 20118228 [patent_doc_number] => 12367943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Reference voltage adjustment per path for high speed memory signaling [patent_app_type] => utility [patent_app_number] => 17/359442 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7670 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359442
Reference voltage adjustment per path for high speed memory signaling Jun 24, 2021 Issued
Array ( [id] => 17158762 [patent_doc_number] => 20210319813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHODS, SEMICONDUCTOR DEVICES, AND SEMICONDUCTOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/358309 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358309
Methods, semiconductor devices, and semiconductor systems Jun 24, 2021 Issued
Array ( [id] => 18175737 [patent_doc_number] => 11575464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Apparatus and method for encoding and decoding channel in communication or broadcasting system [patent_app_type] => utility [patent_app_number] => 17/352713 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 21685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352713
Apparatus and method for encoding and decoding channel in communication or broadcasting system Jun 20, 2021 Issued
Array ( [id] => 17131326 [patent_doc_number] => 20210306095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => USE OF LDPC BASE GRAPHS FOR NR [patent_app_type] => utility [patent_app_number] => 17/345297 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345297
Use of LDPC base graphs for NR Jun 10, 2021 Issued
Array ( [id] => 17296033 [patent_doc_number] => 20210391872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Method and Apparatus for Vertical Layered Decoding of Quasi-Cyclic Low-Density Parity Check Codes Built from Clusters of Circulant Permutation Matrices [patent_app_type] => utility [patent_app_number] => 17/344689 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344689
Method and apparatus for vertical layered decoding of quasi-cyclic low-density parity check codes built from clusters of circulant permutation matrices Jun 9, 2021 Issued
Array ( [id] => 18316416 [patent_doc_number] => 11630497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Transmission of pulse power and data over a wire pair [patent_app_type] => utility [patent_app_number] => 17/340245 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340245
Transmission of pulse power and data over a wire pair Jun 6, 2021 Issued
Array ( [id] => 18236648 [patent_doc_number] => 11601220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Transmitter apparatus and signal processing method thereof [patent_app_type] => utility [patent_app_number] => 17/333520 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 65560 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 509 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333520
Transmitter apparatus and signal processing method thereof May 27, 2021 Issued
Array ( [id] => 17098882 [patent_doc_number] => 20210286673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => Coexisting Differing Erasure Codes [patent_app_type] => utility [patent_app_number] => 17/327250 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17327250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/327250
Coexisting differing erasure codes May 20, 2021 Issued
Array ( [id] => 17942408 [patent_doc_number] => 11476874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Method and system for facilitating a storage server with hybrid memory for journaling and data storage [patent_app_type] => utility [patent_app_number] => 17/320970 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320970
Method and system for facilitating a storage server with hybrid memory for journaling and data storage May 13, 2021 Issued
Array ( [id] => 18303393 [patent_doc_number] => 11625296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => DRAM assist error correction mechanism for DDR SDRAM interface [patent_app_type] => utility [patent_app_number] => 17/319844 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8706 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319844
DRAM assist error correction mechanism for DDR SDRAM interface May 12, 2021 Issued
Array ( [id] => 18072638 [patent_doc_number] => 11531472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Scalable memory system protocol supporting programmable number of levels of indirection [patent_app_type] => utility [patent_app_number] => 17/242037 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 22780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242037
Scalable memory system protocol supporting programmable number of levels of indirection Apr 26, 2021 Issued
Array ( [id] => 18052898 [patent_doc_number] => 11526280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Scalable memory system protocol supporting programmable number of levels of indirection [patent_app_type] => utility [patent_app_number] => 17/241993 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 22697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241993
Scalable memory system protocol supporting programmable number of levels of indirection Apr 26, 2021 Issued
Array ( [id] => 17846711 [patent_doc_number] => 11436084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Semiconductor device having error correction code (ECC) circuit [patent_app_type] => utility [patent_app_number] => 17/239471 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 10723 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239471
Semiconductor device having error correction code (ECC) circuit Apr 22, 2021 Issued
Array ( [id] => 17846710 [patent_doc_number] => 11436083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Data address management in non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/215942 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 36200 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215942
Data address management in non-volatile memory Mar 28, 2021 Issued
Array ( [id] => 17216320 [patent_doc_number] => 20210349658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/210008 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210008
Non-volatile memory module architecture to support memory error correction Mar 22, 2021 Issued
Array ( [id] => 17717251 [patent_doc_number] => 11381254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => High throughput and area efficient partial parallel hard decoder for low-density parity-check codes [patent_app_type] => utility [patent_app_number] => 17/198463 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198463
High throughput and area efficient partial parallel hard decoder for low-density parity-check codes Mar 10, 2021 Issued
Array ( [id] => 17100955 [patent_doc_number] => 20210288746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => Error Correction for LDPC Decoders [patent_app_type] => utility [patent_app_number] => 17/197217 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197217
Error Correction for LDPC Decoders Mar 9, 2021 Abandoned
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