
Esaw T. Abraham
Examiner (ID: 6959)
| Most Active Art Unit | 2112 |
| Art Unit(s) | 2133, 2784, 2112 |
| Total Applications | 1805 |
| Issued Applications | 1618 |
| Pending Applications | 116 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19886691
[patent_doc_number] => 12272416
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => ATPG testing method for latch based memories, for area reduction
[patent_app_type] => utility
[patent_app_number] => 18/661914
[patent_app_country] => US
[patent_app_date] => 2024-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 9085
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661914
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/661914 | ATPG testing method for latch based memories, for area reduction | May 12, 2024 | Issued |
Array
(
[id] => 19532663
[patent_doc_number] => 20240356565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/643302
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643302 | ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT | Apr 22, 2024 | Pending |
Array
(
[id] => 19382820
[patent_doc_number] => 20240272690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => TRANSMISSION OF PULSE POWER AND DATA OVER A WIRE PAIR
[patent_app_type] => utility
[patent_app_number] => 18/643013
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7623
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643013
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643013 | Transmission of pulse power and data over a wire pair | Apr 22, 2024 | Issued |
Array
(
[id] => 19532663
[patent_doc_number] => 20240356565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/643302
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643302 | ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT | Apr 22, 2024 | Pending |
Array
(
[id] => 19560774
[patent_doc_number] => 20240372566
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => SELECTIVE MODE ERROR CONTROL
[patent_app_type] => utility
[patent_app_number] => 18/639692
[patent_app_country] => US
[patent_app_date] => 2024-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639692
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/639692 | SELECTIVE MODE ERROR CONTROL | Apr 17, 2024 | Pending |
Array
(
[id] => 19347416
[patent_doc_number] => 20240256379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SYSTEMS AND METHODS FOR BLOCKCHAIN REPAIR ASSURANCE TOKENS
[patent_app_type] => utility
[patent_app_number] => 18/629317
[patent_app_country] => US
[patent_app_date] => 2024-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8114
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629317
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/629317 | Systems and methods for blockchain repair assurance tokens | Apr 7, 2024 | Issued |
Array
(
[id] => 19347416
[patent_doc_number] => 20240256379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SYSTEMS AND METHODS FOR BLOCKCHAIN REPAIR ASSURANCE TOKENS
[patent_app_type] => utility
[patent_app_number] => 18/629317
[patent_app_country] => US
[patent_app_date] => 2024-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8114
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629317
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/629317 | Systems and methods for blockchain repair assurance tokens | Apr 7, 2024 | Issued |
Array
(
[id] => 19943440
[patent_doc_number] => 12315576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Background reads for solid state storage
[patent_app_type] => utility
[patent_app_number] => 18/623342
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 32458
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623342
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623342 | Background reads for solid state storage | Mar 31, 2024 | Issued |
Array
(
[id] => 20036973
[patent_doc_number] => 20250175195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/620595
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620595
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/620595 | Coding circuit and memory device including the same | Mar 27, 2024 | Issued |
Array
(
[id] => 19303425
[patent_doc_number] => 20240232005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => Efficient Networking for a Distributed Storage System
[patent_app_type] => utility
[patent_app_number] => 18/614833
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8246
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614833
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614833 | Efficient networking for a distributed storage system | Mar 24, 2024 | Issued |
Array
(
[id] => 20249823
[patent_doc_number] => 20250298692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => TRACKING MEMORY DEFECTS USING A SHARED MEMORY DEFECT LIST
[patent_app_type] => utility
[patent_app_number] => 18/610718
[patent_app_country] => US
[patent_app_date] => 2024-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1133
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610718
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/610718 | TRACKING MEMORY DEFECTS USING A SHARED MEMORY DEFECT LIST | Mar 19, 2024 | Pending |
Array
(
[id] => 20249823
[patent_doc_number] => 20250298692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => TRACKING MEMORY DEFECTS USING A SHARED MEMORY DEFECT LIST
[patent_app_type] => utility
[patent_app_number] => 18/610718
[patent_app_country] => US
[patent_app_date] => 2024-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1133
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610718
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/610718 | TRACKING MEMORY DEFECTS USING A SHARED MEMORY DEFECT LIST | Mar 19, 2024 | Pending |
Array
(
[id] => 19629858
[patent_doc_number] => 20240408307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => CRC Interleaving Pattern for Polar Codes
[patent_app_type] => utility
[patent_app_number] => 18/608154
[patent_app_country] => US
[patent_app_date] => 2024-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 40271
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608154
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/608154 | CRC interleaving pattern for polar codes | Mar 17, 2024 | Issued |
Array
(
[id] => 20403547
[patent_doc_number] => 12493520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-09
[patent_title] => Memory system generating error correction code parity based on rank
[patent_app_type] => utility
[patent_app_number] => 18/604940
[patent_app_country] => US
[patent_app_date] => 2024-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 5860
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604940
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604940 | Memory system generating error correction code parity based on rank | Mar 13, 2024 | Issued |
Array
(
[id] => 20011873
[patent_doc_number] => 20250150095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => APPARATUS AND METHOD FOR POWER REDUCTION IN A BIT FLIPPING DECODER
[patent_app_type] => utility
[patent_app_number] => 18/603215
[patent_app_country] => US
[patent_app_date] => 2024-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10352
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603215
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/603215 | APPARATUS AND METHOD FOR POWER REDUCTION IN A BIT FLIPPING DECODER | Mar 12, 2024 | Pending |
Array
(
[id] => 20011873
[patent_doc_number] => 20250150095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => APPARATUS AND METHOD FOR POWER REDUCTION IN A BIT FLIPPING DECODER
[patent_app_type] => utility
[patent_app_number] => 18/603215
[patent_app_country] => US
[patent_app_date] => 2024-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10352
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603215
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/603215 | APPARATUS AND METHOD FOR POWER REDUCTION IN A BIT FLIPPING DECODER | Mar 12, 2024 | Pending |
Array
(
[id] => 19267646
[patent_doc_number] => 20240211349
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => Trait Based Storage Unit Groups
[patent_app_type] => utility
[patent_app_number] => 18/601224
[patent_app_country] => US
[patent_app_date] => 2024-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33026
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601224
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/601224 | Trait based storage unit groups | Mar 10, 2024 | Issued |
Array
(
[id] => 19452423
[patent_doc_number] => 20240312553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAME
[patent_app_type] => utility
[patent_app_number] => 18/598832
[patent_app_country] => US
[patent_app_date] => 2024-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13177
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598832
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/598832 | Apparatuses, systems, and methods for storing error information and providing recommendations based on same | Mar 6, 2024 | Issued |
Array
(
[id] => 19336269
[patent_doc_number] => 20240250699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => MANAGING ERROR CONTROL INFORMATION USING A REGISTER
[patent_app_type] => utility
[patent_app_number] => 18/594795
[patent_app_country] => US
[patent_app_date] => 2024-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20737
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594795
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/594795 | MANAGING ERROR CONTROL INFORMATION USING A REGISTER | Mar 3, 2024 | Pending |
Array
(
[id] => 19385539
[patent_doc_number] => 20240275409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => DATA INTERLEAVING METHOD AND DATA INTERLEAVING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/593519
[patent_app_country] => US
[patent_app_date] => 2024-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 57140
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593519
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/593519 | Data interleaving method and data interleaving apparatus | Feb 29, 2024 | Issued |