Search

Esaw T. Abraham

Examiner (ID: 18736, Phone: (571)272-3812 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2133, 2112, 2784
Total Applications
1849
Issued Applications
1647
Pending Applications
120
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20773302 [patent_doc_number] => 12656975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism [patent_app_type] => utility [patent_app_number] => 18/743629 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743629
Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism Jun 13, 2024 Issued
Array ( [id] => 20690846 [patent_doc_number] => 12621009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Memory, memory module, memory system, and operation method of memory system [patent_app_type] => utility [patent_app_number] => 18/738065 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2772 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738065 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738065
Memory, memory module, memory system, and operation method of memory system Jun 9, 2024 Issued
Array ( [id] => 19635392 [patent_doc_number] => 20240413841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION [patent_app_type] => utility [patent_app_number] => 18/738499 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738499
APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION Jun 9, 2024 Pending
Array ( [id] => 19617486 [patent_doc_number] => 20240403166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => METHOD, APPARATUS AND A NON-TRANSITORY MACHINE-READABLE STORAGE MEDIUM INCLUDING FIRMWARE FOR A CXL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/735239 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735239 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735239
METHOD, APPARATUS AND A NON-TRANSITORY MACHINE-READABLE STORAGE MEDIUM INCLUDING FIRMWARE FOR A CXL MEMORY DEVICE Jun 5, 2024 Pending
Array ( [id] => 19485272 [patent_doc_number] => 20240333314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DECODING DEVICE [patent_app_type] => utility [patent_app_number] => 18/734882 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734882
Error correction decoding device Jun 4, 2024 Issued
Array ( [id] => 19620235 [patent_doc_number] => 20240405915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => POLAR DECODER AND ASSOCIATED METHOD [patent_app_type] => utility [patent_app_number] => 18/734486 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734486
Polar decoder and associated method Jun 4, 2024 Issued
Array ( [id] => 20395383 [patent_doc_number] => 20250370858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => NON-VOLATILE MEMORY METADATA PROTECTION [patent_app_type] => utility [patent_app_number] => 18/733037 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733037 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733037
NON-VOLATILE MEMORY METADATA PROTECTION Jun 3, 2024 Pending
Array ( [id] => 20775388 [patent_doc_number] => 12659074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Communication method, apparatus, and system [patent_app_type] => utility [patent_app_number] => 18/673590 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 18038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673590
Communication method, apparatus, and system May 23, 2024 Issued
Array ( [id] => 20440356 [patent_doc_number] => 12511192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Information broadcast techniques for stacked memory architectures [patent_app_type] => utility [patent_app_number] => 18/667799 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667799
Information broadcast techniques for stacked memory architectures May 16, 2024 Issued
Array ( [id] => 20440356 [patent_doc_number] => 12511192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Information broadcast techniques for stacked memory architectures [patent_app_type] => utility [patent_app_number] => 18/667799 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667799
Information broadcast techniques for stacked memory architectures May 16, 2024 Issued
Array ( [id] => 20403838 [patent_doc_number] => 12493814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Permanent defect qubit repair system and method using built-in-self-repair model at quantum circuit level [patent_app_type] => utility [patent_app_number] => 18/664870 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664870
Permanent defect qubit repair system and method using built-in-self-repair model at quantum circuit level May 14, 2024 Issued
Array ( [id] => 19886691 [patent_doc_number] => 12272416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => ATPG testing method for latch based memories, for area reduction [patent_app_type] => utility [patent_app_number] => 18/661914 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9085 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661914
ATPG testing method for latch based memories, for area reduction May 12, 2024 Issued
Array ( [id] => 19532663 [patent_doc_number] => 20240356565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/643302 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643302
Error correction code (ECC) circuit including low-density parity-check decoder in adaptive operation mode, operating method of the ECC circuit, and memory controller including the ECC circuit Apr 22, 2024 Issued
Array ( [id] => 19382820 [patent_doc_number] => 20240272690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => TRANSMISSION OF PULSE POWER AND DATA OVER A WIRE PAIR [patent_app_type] => utility [patent_app_number] => 18/643013 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643013
Transmission of pulse power and data over a wire pair Apr 22, 2024 Issued
Array ( [id] => 20565258 [patent_doc_number] => 12567873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Selective mode error control [patent_app_type] => utility [patent_app_number] => 18/639692 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7001 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639692
Selective mode error control Apr 17, 2024 Issued
Array ( [id] => 19347416 [patent_doc_number] => 20240256379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SYSTEMS AND METHODS FOR BLOCKCHAIN REPAIR ASSURANCE TOKENS [patent_app_type] => utility [patent_app_number] => 18/629317 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629317 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629317
Systems and methods for blockchain repair assurance tokens Apr 7, 2024 Issued
Array ( [id] => 19943440 [patent_doc_number] => 12315576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Background reads for solid state storage [patent_app_type] => utility [patent_app_number] => 18/623342 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 32458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623342 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623342
Background reads for solid state storage Mar 31, 2024 Issued
Array ( [id] => 20036973 [patent_doc_number] => 20250175195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/620595 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620595
Coding circuit and memory device including the same Mar 27, 2024 Issued
Array ( [id] => 19303425 [patent_doc_number] => 20240232005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => Efficient Networking for a Distributed Storage System [patent_app_type] => utility [patent_app_number] => 18/614833 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614833
Efficient networking for a distributed storage system Mar 24, 2024 Issued
Array ( [id] => 20249823 [patent_doc_number] => 20250298692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TRACKING MEMORY DEFECTS USING A SHARED MEMORY DEFECT LIST [patent_app_type] => utility [patent_app_number] => 18/610718 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610718
Tracking memory defects using a shared memory defect list Mar 19, 2024 Issued
Menu