Esaw T. Abraham

Array ( [id] => 19084824 [patent_doc_number] => 20240111625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING [patent_app_type] => utility [patent_app_number] => 18/233250 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19314211 [patent_doc_number] => 12040035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Buffer circuit with adaptive repair capability [patent_app_type] => utility [patent_app_number] => 18/233257 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19704733 [patent_doc_number] => 12198779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Non-volatile memory and memory system [patent_app_type] => utility [patent_app_number] => 18/447108 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 18702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20242864 [patent_doc_number] => 12423183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Peripheral component interconnect express interface device and system including the same [patent_app_type] => utility [patent_app_number] => 18/446489 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18974973 [patent_doc_number] => 20240055065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/230151 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18882640 [patent_doc_number] => 20240006009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => DATA INPUT VERIFICATION METHOD AND DATA INPUT VERIFICATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/363874 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007475 [patent_doc_number] => 20240071546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY INPUT/OUTPUT [patent_app_type] => utility [patent_app_number] => 18/227545 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19935751 [patent_doc_number] => 12308963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Polar coding techniques for higher-order modulation schemes [patent_app_type] => utility [patent_app_number] => 18/359235 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22917 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18789057 [patent_doc_number] => 20230377670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY ARRAY TEST METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/358202 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19905383 [patent_doc_number] => 12282388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Memory module for detecting and correcting a row direction error and a column direction error [patent_app_type] => utility [patent_app_number] => 18/357930 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19175875 [patent_doc_number] => 20240161849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => WORD LINE LAYER DEPENDENT STRESS AND SCREEN VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/356801 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19295088 [patent_doc_number] => 12034458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-09 [patent_title] => Throughput efficient Reed-Solomon forward error correction decoding [patent_app_type] => utility [patent_app_number] => 18/224403 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19944203 [patent_doc_number] => 12316346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Error processing and correction of adjacent 2-bit errors [patent_app_type] => utility [patent_app_number] => 18/355692 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20130970 [patent_doc_number] => 12373283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Error correction systems and methods for DNA storage [patent_app_type] => utility [patent_app_number] => 18/356104 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19522196 [patent_doc_number] => 12123911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-22 [patent_title] => Integrated circuit with timing correction circuitry [patent_app_type] => utility [patent_app_number] => 18/354925 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20923071 [patent_doc_number] => 12718134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Generating optimal samples in quantum optimization algorithms [patent_app_type] => utility [patent_app_number] => 18/222651 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18956651 [patent_doc_number] => 20240044978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => METHODS FOR DETERMINING AND CALIBRATING NON-LINEARITY IN A PHASE INTERPOLATOR AND RELATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/219484 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20265847 [patent_doc_number] => 12436839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Storage device for setting prohibited threshold voltage distribution [patent_app_type] => utility [patent_app_number] => 18/346671 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6909 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19686876 [patent_doc_number] => 20250005421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => UNIVERSAL FAULT-TOLERANT QUANTUM COMPUTATION WITH A 2D ABELIAN TOPOLOGICAL STABILIZER CODE USING MAGIC PATCHES [patent_app_type] => utility [patent_app_number] => 18/344587 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19782102 [patent_doc_number] => 12231149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Method, apparatus, and device for decoding error correction code, and storage medium [patent_app_type] => utility [patent_app_number] => 18/344604 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7333 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344604 [rel_patent_id] =>[rel_patent_doc_number] =>)