
Ethel R. Cross
Examiner (ID: 12818)
| Most Active Art Unit | 3402 |
| Art Unit(s) | 3402, 1306, 3711, 2305 |
| Total Applications | 964 |
| Issued Applications | 922 |
| Pending Applications | 1 |
| Abandoned Applications | 41 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20649580
[patent_doc_number] => 12604543
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-14
[patent_title] => Manufacturing method of image sensor package
[patent_app_type] => utility
[patent_app_number] => 18/141295
[patent_app_country] => US
[patent_app_date] => 2023-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6126
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141295
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/141295 | Manufacturing method of image sensor package | Apr 27, 2023 | Issued |
Array
(
[id] => 19494310
[patent_doc_number] => 12113034
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Vertical conductive structure surrounded by guard ring and method of making
[patent_app_type] => utility
[patent_app_number] => 18/138865
[patent_app_country] => US
[patent_app_date] => 2023-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10375
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138865
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/138865 | Vertical conductive structure surrounded by guard ring and method of making | Apr 24, 2023 | Issued |
Array
(
[id] => 19524137
[patent_doc_number] => 12125877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Nanostructure field-effect transistor device with dielectric layer for reducing substrate leakage or well isolation leakage and methods of forming
[patent_app_type] => utility
[patent_app_number] => 18/306629
[patent_app_country] => US
[patent_app_date] => 2023-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 54
[patent_no_of_words] => 12669
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306629
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306629 | Nanostructure field-effect transistor device with dielectric layer for reducing substrate leakage or well isolation leakage and methods of forming | Apr 24, 2023 | Issued |
Array
(
[id] => 19460228
[patent_doc_number] => 12100738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-24
[patent_title] => Semiconductor device with implant and method of manufacturing same
[patent_app_type] => utility
[patent_app_number] => 18/306851
[patent_app_country] => US
[patent_app_date] => 2023-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 25
[patent_no_of_words] => 10609
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306851
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306851 | Semiconductor device with implant and method of manufacturing same | Apr 24, 2023 | Issued |
Array
(
[id] => 19531845
[patent_doc_number] => 20240355747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => SUBSTRATE WITH MULTIPLE CORE LAYERS TO PROVIDE VARIED THICKNESS CAVITIES SUPPORTING VARIED THICKNESS EMBEDDED ELECTRICAL DEVICES, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS
[patent_app_type] => utility
[patent_app_number] => 18/304195
[patent_app_country] => US
[patent_app_date] => 2023-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19502
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304195
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/304195 | Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods | Apr 19, 2023 | Issued |
Array
(
[id] => 18812743
[patent_doc_number] => 20230387080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/303360
[patent_app_country] => US
[patent_app_date] => 2023-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6527
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303360
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/303360 | Semiconductor package and method for fabricating the same | Apr 18, 2023 | Issued |
Array
(
[id] => 19627245
[patent_doc_number] => 12166096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => Semiconductor device structure with uneven gate profile
[patent_app_type] => utility
[patent_app_number] => 18/301554
[patent_app_country] => US
[patent_app_date] => 2023-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 34
[patent_no_of_words] => 9681
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301554
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/301554 | Semiconductor device structure with uneven gate profile | Apr 16, 2023 | Issued |
Array
(
[id] => 18821321
[patent_doc_number] => 20230395662
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/299086
[patent_app_country] => US
[patent_app_date] => 2023-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10092
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299086
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/299086 | Semiconductor transistor devices including alternatively stacked source/drain regions | Apr 11, 2023 | Issued |
Array
(
[id] => 20734580
[patent_doc_number] => 12641845
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-26
[patent_title] => Semiconductor contact structure including via structure with metal bulk layer nested within barrier liner and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/299294
[patent_app_country] => US
[patent_app_date] => 2023-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 48
[patent_no_of_words] => 12067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299294
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/299294 | Semiconductor contact structure including via structure with metal bulk layer nested within barrier liner and method for forming the same | Apr 11, 2023 | Issued |
Array
(
[id] => 19428402
[patent_doc_number] => 12087839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Transistor gate electrodes with voids
[patent_app_type] => utility
[patent_app_number] => 18/299438
[patent_app_country] => US
[patent_app_date] => 2023-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 55
[patent_no_of_words] => 14548
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299438
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/299438 | Transistor gate electrodes with voids | Apr 11, 2023 | Issued |
Array
(
[id] => 20276458
[patent_doc_number] => 12446247
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Circuit cell for a standard cell semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/298820
[patent_app_country] => US
[patent_app_date] => 2023-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3807
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298820
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/298820 | Circuit cell for a standard cell semiconductor device | Apr 10, 2023 | Issued |
Array
(
[id] => 18540971
[patent_doc_number] => 20230246083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => PROTECTIVE LINER FOR SOURCE/DRAIN CONTACT TO PREVENT ELECTRICAL BRIDGING WHILE MINIMIZING RESISTANCE
[patent_app_type] => utility
[patent_app_number] => 18/297892
[patent_app_country] => US
[patent_app_date] => 2023-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9407
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297892
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/297892 | Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance | Apr 9, 2023 | Issued |
Array
(
[id] => 18533208
[patent_doc_number] => 20230238284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => Backside Via With A Low-K Spacer
[patent_app_type] => utility
[patent_app_number] => 18/190563
[patent_app_country] => US
[patent_app_date] => 2023-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10183
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190563
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/190563 | Backside via with a low-k spacer | Mar 26, 2023 | Issued |
Array
(
[id] => 18696584
[patent_doc_number] => 20230327025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => Channel Configuration for Improving Multigate Device Performance and Method of Fabrication Thereof
[patent_app_type] => utility
[patent_app_number] => 18/190754
[patent_app_country] => US
[patent_app_date] => 2023-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20985
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190754
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/190754 | Channel configurations with stacked segments for gate-all-around based devices and methods of fabrication thereof | Mar 26, 2023 | Issued |
Array
(
[id] => 19484123
[patent_doc_number] => 20240332165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => OFFSET VIA FORMATION FOR FLEXIBLE ROUTING
[patent_app_type] => utility
[patent_app_number] => 18/126591
[patent_app_country] => US
[patent_app_date] => 2023-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126591
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/126591 | OFFSET VIA FORMATION FOR FLEXIBLE ROUTING | Mar 26, 2023 | Pending |
Array
(
[id] => 19468333
[patent_doc_number] => 20240322003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => SEMICONDUCTOR DEVICE HAVING STRAINED CHANNEL AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/186248
[patent_app_country] => US
[patent_app_date] => 2023-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9119
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186248
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/186248 | Semiconductor device having strained channel and method for manufacturing the same | Mar 19, 2023 | Issued |
Array
(
[id] => 18500657
[patent_doc_number] => 20230223453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-13
[patent_title] => Gate Structure with Desired Profile for Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 18/182928
[patent_app_country] => US
[patent_app_date] => 2023-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8022
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182928
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/182928 | Gate structure with non-linear profile for transistors | Mar 12, 2023 | Issued |
Array
(
[id] => 19371663
[patent_doc_number] => 12063768
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Transistors with multiple threshold voltages
[patent_app_type] => utility
[patent_app_number] => 18/182837
[patent_app_country] => US
[patent_app_date] => 2023-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 10491
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182837
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/182837 | Transistors with multiple threshold voltages | Mar 12, 2023 | Issued |
Array
(
[id] => 20675282
[patent_doc_number] => 12615815
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-28
[patent_title] => Semiconductor structure including dielectric wall and spacer layer and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/177996
[patent_app_country] => US
[patent_app_date] => 2023-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 35
[patent_no_of_words] => 10697
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177996
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/177996 | Semiconductor structure including dielectric wall and spacer layer and method for forming the same | Mar 2, 2023 | Issued |
Array
(
[id] => 20637900
[patent_doc_number] => 12598797
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Gate spacers in semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 18/177911
[patent_app_country] => US
[patent_app_date] => 2023-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 5210
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177911
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/177911 | Gate spacers in semiconductor devices | Mar 2, 2023 | Issued |