
Eugene Lee
Examiner (ID: 1659, Phone: (571)272-1733 , Office: P/2815 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 1444 |
| Issued Applications | 1100 |
| Pending Applications | 119 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
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[patent_title] => Manufacturing method of semiconductor device
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Array
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[patent_title] => STRUCTURE AND METHODS FOR OPTIMIZING THROUGH SUBSTRATE VIAS AND COOLING CHANNELS IN A COMPOSITE SUBSTRATE
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Array
(
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[patent_title] => BONDING SCHEME TO PROVIDE IMPROVED COPLANARITY AND HIGH JOINT YIELDS WITH REDUCED COSTS AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
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Array
(
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[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
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Array
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[patent_title] => SEMICONDUCTOR PACKAGES WITH COMPACT LEAD DESIGN
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Array
(
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Array
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Array
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Array
(
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Array
(
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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