Search

Eugene Lee

Examiner (ID: 1659, Phone: (571)272-1733 , Office: P/2815 )

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
1444
Issued Applications
1100
Pending Applications
119
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19901493 [patent_doc_number] => 12279446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 18/645366 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2329 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645366
Manufacturing method of semiconductor device Apr 23, 2024 Issued
Array ( [id] => 20311982 [patent_doc_number] => 20250329611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => STRUCTURE AND METHODS FOR OPTIMIZING THROUGH SUBSTRATE VIAS AND COOLING CHANNELS IN A COMPOSITE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/643267 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643267
STRUCTURE AND METHODS FOR OPTIMIZING THROUGH SUBSTRATE VIAS AND COOLING CHANNELS IN A COMPOSITE SUBSTRATE Apr 22, 2024 Pending
Array ( [id] => 20312043 [patent_doc_number] => 20250329672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => BONDING SCHEME TO PROVIDE IMPROVED COPLANARITY AND HIGH JOINT YIELDS WITH REDUCED COSTS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/641473 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641473
BONDING SCHEME TO PROVIDE IMPROVED COPLANARITY AND HIGH JOINT YIELDS WITH REDUCED COSTS AND METHODS FOR FORMING THE SAME Apr 21, 2024 Pending
Array ( [id] => 19364387 [patent_doc_number] => 20240266421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/625547 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625547
Semiconductor device and method for manufacturing the same Apr 2, 2024 Issued
Array ( [id] => 20283842 [patent_doc_number] => 20250309084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SEMICONDUCTOR PACKAGES WITH COMPACT LEAD DESIGN [patent_app_type] => utility [patent_app_number] => 18/622547 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622547
SEMICONDUCTOR PACKAGES WITH COMPACT LEAD DESIGN Mar 28, 2024 Pending
Array ( [id] => 19502123 [patent_doc_number] => 20240341141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/620890 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620890
DISPLAY DEVICE Mar 27, 2024 Pending
Array ( [id] => 19484388 [patent_doc_number] => 20240332430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/618797 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618797 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618797
SEMICONDUCTOR DEVICE Mar 26, 2024 Pending
Array ( [id] => 20251207 [patent_doc_number] => 20250300076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => STACKED COMPLIMENTARY METAL-OXIDE SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/611804 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611804
STACKED COMPLIMENTARY METAL-OXIDE SEMICONDUCTOR STRUCTURE Mar 20, 2024 Pending
Array ( [id] => 19788561 [patent_doc_number] => 20250062240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR PACKAGE WITH IMPROVED STRUCTURAL STABILITY [patent_app_type] => utility [patent_app_number] => 18/611488 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611488
SEMICONDUCTOR PACKAGE WITH IMPROVED STRUCTURAL STABILITY Mar 19, 2024 Pending
Array ( [id] => 20111530 [patent_doc_number] => 12362266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Low stress asymmetric dual side module [patent_app_type] => utility [patent_app_number] => 18/595569 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 1197 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595569
Low stress asymmetric dual side module Mar 4, 2024 Issued
Array ( [id] => 19980267 [patent_doc_number] => 12347755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Low stress asymmetric dual side module [patent_app_type] => utility [patent_app_number] => 18/592704 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 1196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592704 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/592704
Low stress asymmetric dual side module Feb 29, 2024 Issued
Array ( [id] => 19321513 [patent_doc_number] => 20240243060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYERS HAVING DIFFERENT PATTERN DENSITIES AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/581813 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581813 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581813
SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYERS HAVING DIFFERENT PATTERN DENSITIES AND METHOD FOR FABRICATING THE SAME Feb 19, 2024 Abandoned
Array ( [id] => 19751883 [patent_doc_number] => 20250040448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => A-axis Josephson Junctions with Improved Contacts [patent_app_type] => utility [patent_app_number] => 18/442149 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442149
A-axis Josephson junctions with improved contacts Feb 14, 2024 Issued
Array ( [id] => 19221519 [patent_doc_number] => 20240186223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 18/440915 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440915 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440915
Semiconductor device package Feb 12, 2024 Issued
Array ( [id] => 19823444 [patent_doc_number] => 20250081651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => IMAGE SENSING DEVICE INCLUDING SLOPED ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/433254 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433254 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433254
IMAGE SENSING DEVICE INCLUDING SLOPED ISOLATION STRUCTURE Feb 4, 2024 Pending
Array ( [id] => 19823235 [patent_doc_number] => 20250081442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/429438 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429438 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429438
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Jan 31, 2024 Pending
Array ( [id] => 19146495 [patent_doc_number] => 20240145525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => DISPLAY MODULE AND WEARABLE ELECTRONIC DEVICE COMPRISING SAME [patent_app_type] => utility [patent_app_number] => 18/407986 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407986
DISPLAY MODULE AND WEARABLE ELECTRONIC DEVICE COMPRISING SAME Jan 8, 2024 Pending
Array ( [id] => 20091059 [patent_doc_number] => 20250220995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SILICON CARBIDE BASED SEMICONDUCTOR DEVICES WITH RING-SHAPED CHANNEL REGIONS AND/OR CHANNEL REGIONS THAT EXTEND IN MULTIPLE DIRECTIONS IN PLAN VIEW [patent_app_type] => utility [patent_app_number] => 18/403068 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403068
SILICON CARBIDE BASED SEMICONDUCTOR DEVICES WITH RING-SHAPED CHANNEL REGIONS AND/OR CHANNEL REGIONS THAT EXTEND IN MULTIPLE DIRECTIONS IN PLAN VIEW Jan 2, 2024 Pending
Array ( [id] => 19879778 [patent_doc_number] => 20250112035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => HYBRID SEMICONDUCTOR WAFER AND METHOD OF FORMING [patent_app_type] => utility [patent_app_number] => 18/401902 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401902
HYBRID SEMICONDUCTOR WAFER AND METHOD OF FORMING Jan 1, 2024 Pending
Array ( [id] => 20091046 [patent_doc_number] => 20250220982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MONOLITHIC BIDIRECTIONAL JFET SWITCH [patent_app_type] => utility [patent_app_number] => 18/399226 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399226
MONOLITHIC BIDIRECTIONAL JFET SWITCH Dec 27, 2023 Pending
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