Search

Euncha P. Cherry

Examiner (ID: 6173, Phone: (571)272-2310 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2872
Total Applications
2394
Issued Applications
2091
Pending Applications
97
Abandoned Applications
243

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11733067 [patent_doc_number] => 20170194510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH REPLACEMENT SPACER' [patent_app_type] => utility [patent_app_number] => 15/467555 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467555
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer Mar 22, 2017 Issued
Array ( [id] => 12040479 [patent_doc_number] => 09818713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Structures and methods for low temperature bonding using nanoparticles' [patent_app_type] => utility [patent_app_number] => 15/462360 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 13755 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462360
Structures and methods for low temperature bonding using nanoparticles Mar 16, 2017 Issued
Array ( [id] => 11710790 [patent_doc_number] => 20170179289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD TO FORM STRAINED nFET AND STRAINED pFET NANOWIRES ON A SAME SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/450756 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6446 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450756 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450756
Method to form strained nFET and strained pFET nanowires on a same substrate Mar 5, 2017 Issued
Array ( [id] => 12477882 [patent_doc_number] => 09991215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-05 [patent_title] => Semiconductor structure with through substrate via and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/410430 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5890 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410430
Semiconductor structure with through substrate via and manufacturing method thereof Jan 18, 2017 Issued
Array ( [id] => 13321283 [patent_doc_number] => 20180212179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => OLED DISPLAY PANEL AND MANUFACTURE METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/503715 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15503715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/503715
OLED DISPLAY PANEL AND MANUFACTURE METHOD THEREOF Dec 28, 2016 Abandoned
Array ( [id] => 13653783 [patent_doc_number] => 09853214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Resistive random access memory device with reduced power consumption [patent_app_type] => utility [patent_app_number] => 15/393983 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4297 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393983
Resistive random access memory device with reduced power consumption Dec 28, 2016 Issued
Array ( [id] => 14398235 [patent_doc_number] => 10312411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Light-emitting element, light-emitting element unit, and light-emitting element package [patent_app_type] => utility [patent_app_number] => 15/387925 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 14135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387925 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387925
Light-emitting element, light-emitting element unit, and light-emitting element package Dec 21, 2016 Issued
Array ( [id] => 11544906 [patent_doc_number] => 20170098731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'Light Emitting Heterostructure with Partially Relaxed Semiconductor Layer' [patent_app_type] => utility [patent_app_number] => 15/387575 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387575
Light emitting heterostructure with partially relaxed semiconductor layer Dec 20, 2016 Issued
Array ( [id] => 12554517 [patent_doc_number] => 10014397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Bipolar junction transistors with a combined vertical-lateral architecture [patent_app_type] => utility [patent_app_number] => 15/383171 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6588 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383171
Bipolar junction transistors with a combined vertical-lateral architecture Dec 18, 2016 Issued
Array ( [id] => 11718301 [patent_doc_number] => 20170186800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'IMAGING DEVICE AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/383327 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 34510 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383327
Imaging device and electronic device using three dimentional (3D) integration Dec 18, 2016 Issued
Array ( [id] => 11718377 [patent_doc_number] => 20170186875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/383478 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 42540 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383478 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383478
Semiconductor device and method for manufacturing the same Dec 18, 2016 Issued
Array ( [id] => 12047575 [patent_doc_number] => 09825185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures' [patent_app_type] => utility [patent_app_number] => 15/383048 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383048 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383048
Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures Dec 18, 2016 Issued
Array ( [id] => 11544756 [patent_doc_number] => 20170098581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'GATE STRUCTURES WITH VARIOUS WIDTHS AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/383837 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383837 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383837
Gate structures with various widths and method for forming the same Dec 18, 2016 Issued
Array ( [id] => 12498729 [patent_doc_number] => 09997537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Semiconductor devices including gate insulation layers on channel materials and methods of forming the same [patent_app_type] => utility [patent_app_number] => 15/375387 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375387
Semiconductor devices including gate insulation layers on channel materials and methods of forming the same Dec 11, 2016 Issued
Array ( [id] => 12969442 [patent_doc_number] => 09876055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-23 [patent_title] => Three-dimensional semiconductor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/367390 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 47 [patent_no_of_words] => 5418 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367390
Three-dimensional semiconductor device and method for forming the same Dec 1, 2016 Issued
Array ( [id] => 12535191 [patent_doc_number] => 10008590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Semiconductor device with trench edge termination [patent_app_type] => utility [patent_app_number] => 15/367633 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9749 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367633 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367633
Semiconductor device with trench edge termination Dec 1, 2016 Issued
Array ( [id] => 12202424 [patent_doc_number] => 09905496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Wiring circuit board and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/367494 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 10201 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367494 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367494
Wiring circuit board and method of manufacturing the same Dec 1, 2016 Issued
Array ( [id] => 13043645 [patent_doc_number] => 10043966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Semiconductor device including via plugs [patent_app_type] => utility [patent_app_number] => 15/367536 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16303 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367536
Semiconductor device including via plugs Dec 1, 2016 Issued
Array ( [id] => 11876633 [patent_doc_number] => 09748415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Fast process flow, on-wafer interconnection and singulation for MEPV' [patent_app_type] => utility [patent_app_number] => 15/360553 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6600 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/360553
Fast process flow, on-wafer interconnection and singulation for MEPV Nov 22, 2016 Issued
Array ( [id] => 11404911 [patent_doc_number] => 20170025448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'DRIVER CIRCUIT AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/285661 [patent_app_country] => US [patent_app_date] => 2016-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22524 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15285661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/285661
Driver circuit with oxide semiconductor layers having varying hydrogen concentrations Oct 4, 2016 Issued
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