Eunja Adolphe

Array ( [id] => 3955859 [patent_doc_number] => 05999033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Low-to-high voltage CMOS driver circuit for driving capacitive loads' [patent_app_type] => 1 [patent_app_number] => 9/231853 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999033.pdf [firstpage_image] =>[orig_patent_app_number] => 231853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4229487 [patent_doc_number] => 06011417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Auto zero circuitry and associated method' [patent_app_type] => 1 [patent_app_number] => 9/153747 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2522 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011417.pdf [firstpage_image] =>[orig_patent_app_number] => 153747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3920147 [patent_doc_number] => 06002286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Apparatus and method for a programmable interval timing generator in a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/127391 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2877 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002286.pdf [firstpage_image] =>[orig_patent_app_number] => 127391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3955845 [patent_doc_number] => 05999032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Multiple phase synchronous race delay clock distribution circuit with skew compensation' [patent_app_type] => 1 [patent_app_number] => 9/035053 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5734 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999032.pdf [firstpage_image] =>[orig_patent_app_number] => 035053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4141689 [patent_doc_number] => 06016069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Attenuating systems and methods for acquiring synchronization in phase locked loops' [patent_app_type] => 1 [patent_app_number] => 9/021668 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3539 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016069.pdf [firstpage_image] =>[orig_patent_app_number] => 021668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011757 [patent_doc_number] => 06005425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'PLL using pulse width detection for frequency and phase error correction' [patent_app_type] => 1 [patent_app_number] => 9/018639 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5915 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005425.pdf [firstpage_image] =>[orig_patent_app_number] => 018639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040720 [patent_doc_number] => 05994938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Self-calibrating programmable phase shifter' [patent_app_type] => 1 [patent_app_number] => 9/016757 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6493 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994938.pdf [firstpage_image] =>[orig_patent_app_number] => 016757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040735 [patent_doc_number] => 05994939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Variable delay cell with a self-biasing load' [patent_app_type] => 1 [patent_app_number] => 9/006649 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994939.pdf [firstpage_image] =>[orig_patent_app_number] => 006649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4092846 [patent_doc_number] => 06018259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Phase locked delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/998326 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5565 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018259.pdf [firstpage_image] =>[orig_patent_app_number] => 998326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950482 [patent_doc_number] => 05982212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Delay difference adjustment circuit and phase adjuster' [patent_app_type] => 1 [patent_app_number] => 8/985780 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6566 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982212.pdf [firstpage_image] =>[orig_patent_app_number] => 985780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4033603 [patent_doc_number] => 05903175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'D-type latch circuit and device using the same' [patent_app_type] => 1 [patent_app_number] => 8/970087 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4672 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903175.pdf [firstpage_image] =>[orig_patent_app_number] => 970087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4072838 [patent_doc_number] => 06008671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Clock signal monitoring apparatus' [patent_app_type] => 1 [patent_app_number] => 8/954727 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1958 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008671.pdf [firstpage_image] =>[orig_patent_app_number] => 954727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3982467 [patent_doc_number] => 05917345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Drive signal generating circuit for sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/953555 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917345.pdf [firstpage_image] =>[orig_patent_app_number] => 953555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4205213 [patent_doc_number] => 06014052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Implementation of serial fusible links' [patent_app_type] => 1 [patent_app_number] => 8/939942 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1710 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014052.pdf [firstpage_image] =>[orig_patent_app_number] => 939942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3832345 [patent_doc_number] => 05783950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Phase comparator' [patent_app_type] => 1 [patent_app_number] => 8/939124 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5156 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 809 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783950.pdf [firstpage_image] =>[orig_patent_app_number] => 939124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3956718 [patent_doc_number] => 05955904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Semiconductor integrated circuit with appropriate data output timing and reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 8/931669 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 129 [patent_no_of_words] => 12386 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955904.pdf [firstpage_image] =>[orig_patent_app_number] => 931669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050339 [patent_doc_number] => 05909136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Quarter-square multiplier based on the dynamic bias current technique' [patent_app_type] => 1 [patent_app_number] => 8/928452 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4033 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909136.pdf [firstpage_image] =>[orig_patent_app_number] => 928452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3991272 [patent_doc_number] => 05910744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Variable delaying circuit having a nearly linear delay characteristic' [patent_app_type] => 1 [patent_app_number] => 8/924933 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910744.pdf [firstpage_image] =>[orig_patent_app_number] => 924933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4072969 [patent_doc_number] => 06008680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Continuously adjustable delay-locked loop' [patent_app_type] => 1 [patent_app_number] => 8/919248 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5096 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008680.pdf [firstpage_image] =>[orig_patent_app_number] => 919248 [rel_patent_id] =>[rel_patent_doc_number] =>)