| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3516594
[patent_doc_number] => 05563543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range'
[patent_app_type] => 1
[patent_app_number] => 8/355568
[patent_app_country] => US
[patent_app_date] => 1994-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2267
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/563/05563543.pdf
[firstpage_image] =>[orig_patent_app_number] => 355568
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/355568 | Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range | Dec 13, 1994 | Issued |
Array
(
[id] => 3581245
[patent_doc_number] => 05523711
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Signal delaying outputting circuit'
[patent_app_type] => 1
[patent_app_number] => 8/358592
[patent_app_country] => US
[patent_app_date] => 1994-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 5795
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 498
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/523/05523711.pdf
[firstpage_image] =>[orig_patent_app_number] => 358592
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/358592 | Signal delaying outputting circuit | Dec 13, 1994 | Issued |
Array
(
[id] => 3631651
[patent_doc_number] => 05602676
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Compact zoom lens with reduced aspheric decenter sensitivity'
[patent_app_type] => 1
[patent_app_number] => 8/347612
[patent_app_country] => US
[patent_app_date] => 1994-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6194
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/602/05602676.pdf
[firstpage_image] =>[orig_patent_app_number] => 347612
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/347612 | Compact zoom lens with reduced aspheric decenter sensitivity | Nov 29, 1994 | Issued |
| 08/347805 | MASTER-SLAVE FLIP-FLOP CIRCUIT WITH BYPASS | Nov 29, 1994 | Abandoned |
| 08/343003 | FEEDBACK LATCH AND METHOD THEREFOR | Nov 20, 1994 | Abandoned |
Array
(
[id] => 3555954
[patent_doc_number] => 05572159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Voltage-controlled delay element with programmable delay'
[patent_app_type] => 1
[patent_app_number] => 8/339328
[patent_app_country] => US
[patent_app_date] => 1994-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4303
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/572/05572159.pdf
[firstpage_image] =>[orig_patent_app_number] => 339328
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/339328 | Voltage-controlled delay element with programmable delay | Nov 13, 1994 | Issued |
Array
(
[id] => 3502618
[patent_doc_number] => 05532634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-02
[patent_title] => 'High-integration J-K flip-flop circuit'
[patent_app_type] => 1
[patent_app_number] => 8/339240
[patent_app_country] => US
[patent_app_date] => 1994-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 32
[patent_no_of_words] => 11128
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/532/05532634.pdf
[firstpage_image] =>[orig_patent_app_number] => 339240
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/339240 | High-integration J-K flip-flop circuit | Nov 9, 1994 | Issued |
Array
(
[id] => 3608175
[patent_doc_number] => 05578952
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Fixed-interval timing circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/335616
[patent_app_country] => US
[patent_app_date] => 1994-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 2397
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/578/05578952.pdf
[firstpage_image] =>[orig_patent_app_number] => 335616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/335616 | Fixed-interval timing circuit and method | Nov 7, 1994 | Issued |
Array
(
[id] => 3497242
[patent_doc_number] => 05561383
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Switchable peak/average detect circuit'
[patent_app_type] => 1
[patent_app_number] => 8/334710
[patent_app_country] => US
[patent_app_date] => 1994-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 1005
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/561/05561383.pdf
[firstpage_image] =>[orig_patent_app_number] => 334710
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/334710 | Switchable peak/average detect circuit | Nov 3, 1994 | Issued |
Array
(
[id] => 3497348
[patent_doc_number] => 05561390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Clock signal generation circuit having detective circuit detecting loss of reference clock'
[patent_app_type] => 1
[patent_app_number] => 8/329858
[patent_app_country] => US
[patent_app_date] => 1994-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 5929
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/561/05561390.pdf
[firstpage_image] =>[orig_patent_app_number] => 329858
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/329858 | Clock signal generation circuit having detective circuit detecting loss of reference clock | Oct 26, 1994 | Issued |
Array
(
[id] => 3762002
[patent_doc_number] => 05721503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Flash analog-to-digital converter with latching exclusive or gates'
[patent_app_type] => 1
[patent_app_number] => 8/329565
[patent_app_country] => US
[patent_app_date] => 1994-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5214
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721503.pdf
[firstpage_image] =>[orig_patent_app_number] => 329565
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/329565 | Flash analog-to-digital converter with latching exclusive or gates | Oct 25, 1994 | Issued |
| 08/325480 | DELAY CIRCUIT USING CAPACITOR AND TRANSISTOR | Oct 18, 1994 | Abandoned |
Array
(
[id] => 3522940
[patent_doc_number] => 05506526
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Offset-compensated sample and hold arrangement and method for its operation'
[patent_app_type] => 1
[patent_app_number] => 8/290862
[patent_app_country] => US
[patent_app_date] => 1994-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3224
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/506/05506526.pdf
[firstpage_image] =>[orig_patent_app_number] => 290862
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/290862 | Offset-compensated sample and hold arrangement and method for its operation | Oct 16, 1994 | Issued |
Array
(
[id] => 3497907
[patent_doc_number] => 05537070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Output driver with slew rate control'
[patent_app_type] => 1
[patent_app_number] => 8/323330
[patent_app_country] => US
[patent_app_date] => 1994-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 3305
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/537/05537070.pdf
[firstpage_image] =>[orig_patent_app_number] => 323330
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323330 | Output driver with slew rate control | Oct 13, 1994 | Issued |
Array
(
[id] => 3655499
[patent_doc_number] => 05606276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Method and apparatus for creating a large delay in a pulse in a layout efficient manner'
[patent_app_type] => 1
[patent_app_number] => 8/319381
[patent_app_country] => US
[patent_app_date] => 1994-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2040
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/606/05606276.pdf
[firstpage_image] =>[orig_patent_app_number] => 319381
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319381 | Method and apparatus for creating a large delay in a pulse in a layout efficient manner | Oct 4, 1994 | Issued |
Array
(
[id] => 3530911
[patent_doc_number] => 05528190
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'CMOS input voltage clamp'
[patent_app_type] => 1
[patent_app_number] => 8/316958
[patent_app_country] => US
[patent_app_date] => 1994-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3584
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528190.pdf
[firstpage_image] =>[orig_patent_app_number] => 316958
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/316958 | CMOS input voltage clamp | Oct 2, 1994 | Issued |
Array
(
[id] => 3596111
[patent_doc_number] => 05568072
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Circuit indicating the phase relation between several signals having the same frequency'
[patent_app_type] => 1
[patent_app_number] => 8/317132
[patent_app_country] => US
[patent_app_date] => 1994-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4318
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568072.pdf
[firstpage_image] =>[orig_patent_app_number] => 317132
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/317132 | Circuit indicating the phase relation between several signals having the same frequency | Oct 2, 1994 | Issued |
| 08/317059 | METHOD AND APPARATUS FOR PROVIDING A LOW VOLTAGE LEVEL SHIFT | Oct 2, 1994 | Abandoned |
Array
(
[id] => 3558879
[patent_doc_number] => 05519352
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Integrator system with variable gain feedback'
[patent_app_type] => 1
[patent_app_number] => 8/316283
[patent_app_country] => US
[patent_app_date] => 1994-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/519/05519352.pdf
[firstpage_image] =>[orig_patent_app_number] => 316283
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/316283 | Integrator system with variable gain feedback | Sep 29, 1994 | Issued |
Array
(
[id] => 3535805
[patent_doc_number] => 05583461
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Internal clock signal generation circuit having external clock detection and a selectable internal clock pulse'
[patent_app_type] => 1
[patent_app_number] => 8/308351
[patent_app_country] => US
[patent_app_date] => 1994-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4939
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583461.pdf
[firstpage_image] =>[orig_patent_app_number] => 308351
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308351 | Internal clock signal generation circuit having external clock detection and a selectable internal clock pulse | Sep 18, 1994 | Issued |