| Application number | Title of the application | Filing Date | Status |
|---|
| 08/308456 | MULTISTAGE SWITCHING CIRCUIT | Sep 18, 1994 | Abandoned |
| 08/308148 | HYSTERETIC POWER-UP CIRCUIT | Sep 18, 1994 | Abandoned |
Array
(
[id] => 3532293
[patent_doc_number] => 05541544
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Bipolar flip-flop circuit with improved noise immunity'
[patent_app_type] => 1
[patent_app_number] => 8/307464
[patent_app_country] => US
[patent_app_date] => 1994-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 6285
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541544.pdf
[firstpage_image] =>[orig_patent_app_number] => 307464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/307464 | Bipolar flip-flop circuit with improved noise immunity | Sep 18, 1994 | Issued |
| 08/308022 | REFERENCE CIRCUITRY FOR SENSE AMPLIFIER | Sep 15, 1994 | Abandoned |
Array
(
[id] => 3688094
[patent_doc_number] => 05633608
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Digital delay line'
[patent_app_type] => 1
[patent_app_number] => 8/306488
[patent_app_country] => US
[patent_app_date] => 1994-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3493
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/633/05633608.pdf
[firstpage_image] =>[orig_patent_app_number] => 306488
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/306488 | Digital delay line | Sep 14, 1994 | Issued |
Array
(
[id] => 3530670
[patent_doc_number] => 05504443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Differential latch sense amlifiers using feedback'
[patent_app_type] => 1
[patent_app_number] => 8/301657
[patent_app_country] => US
[patent_app_date] => 1994-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5016
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/504/05504443.pdf
[firstpage_image] =>[orig_patent_app_number] => 301657
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/301657 | Differential latch sense amlifiers using feedback | Sep 6, 1994 | Issued |
| 08/300608 | PHASE-LOCKED DELAY LOOP FOR CLOCK CORRECTION | Sep 1, 1994 | Abandoned |
Array
(
[id] => 3950455
[patent_doc_number] => 05982210
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'PLL system clock generator with instantaneous clock frequency shifting'
[patent_app_type] => 1
[patent_app_number] => 8/300028
[patent_app_country] => US
[patent_app_date] => 1994-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4208
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/982/05982210.pdf
[firstpage_image] =>[orig_patent_app_number] => 300028
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/300028 | PLL system clock generator with instantaneous clock frequency shifting | Sep 1, 1994 | Issued |
Array
(
[id] => 3594526
[patent_doc_number] => 05497114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Flip-flop circuit'
[patent_app_type] => 1
[patent_app_number] => 8/299117
[patent_app_country] => US
[patent_app_date] => 1994-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 5276
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497114.pdf
[firstpage_image] =>[orig_patent_app_number] => 299117
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299117 | Flip-flop circuit | Sep 1, 1994 | Issued |
Array
(
[id] => 3532211
[patent_doc_number] => 05541538
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'High speed comparator'
[patent_app_type] => 1
[patent_app_number] => 8/299741
[patent_app_country] => US
[patent_app_date] => 1994-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2951
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541538.pdf
[firstpage_image] =>[orig_patent_app_number] => 299741
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299741 | High speed comparator | Aug 31, 1994 | Issued |
| 08/298696 | DIFFERENTIAL CHARGE PUMP WITH INTEGRATED COMMON MODE CONTROL | Aug 30, 1994 | Abandoned |
Array
(
[id] => 3592043
[patent_doc_number] => 05552725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Low power, slew rate insensitive power-on reset circuit'
[patent_app_type] => 1
[patent_app_number] => 8/286685
[patent_app_country] => US
[patent_app_date] => 1994-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3250
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/552/05552725.pdf
[firstpage_image] =>[orig_patent_app_number] => 286685
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/286685 | Low power, slew rate insensitive power-on reset circuit | Aug 4, 1994 | Issued |
Array
(
[id] => 3584904
[patent_doc_number] => 05491436
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Compensated CMOS driver circuit with reduced DC losses'
[patent_app_type] => 1
[patent_app_number] => 8/282835
[patent_app_country] => US
[patent_app_date] => 1994-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2537
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491436.pdf
[firstpage_image] =>[orig_patent_app_number] => 282835
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/282835 | Compensated CMOS driver circuit with reduced DC losses | Jul 28, 1994 | Issued |
Array
(
[id] => 3530789
[patent_doc_number] => 05528182
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Power-on signal generating circuit operating with low-dissipation current'
[patent_app_type] => 1
[patent_app_number] => 8/281366
[patent_app_country] => US
[patent_app_date] => 1994-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3959
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528182.pdf
[firstpage_image] =>[orig_patent_app_number] => 281366
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/281366 | Power-on signal generating circuit operating with low-dissipation current | Jul 26, 1994 | Issued |
| 08/277917 | LOW-TO-HIGH VOLTAGE CMOS DRIVER CIRCUIT FOR DRIVING CAPACITIVE LOADS | Jul 19, 1994 | Abandoned |
Array
(
[id] => 3664597
[patent_doc_number] => 05592114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'True type single-phase shift circuit'
[patent_app_type] => 1
[patent_app_number] => 8/275172
[patent_app_country] => US
[patent_app_date] => 1994-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1981
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/592/05592114.pdf
[firstpage_image] =>[orig_patent_app_number] => 275172
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/275172 | True type single-phase shift circuit | Jul 13, 1994 | Issued |
Array
(
[id] => 3448214
[patent_doc_number] => 05467039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Chip initialization signal generating circuit'
[patent_app_type] => 1
[patent_app_number] => 8/268523
[patent_app_country] => US
[patent_app_date] => 1994-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2332
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467039.pdf
[firstpage_image] =>[orig_patent_app_number] => 268523
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/268523 | Chip initialization signal generating circuit | Jul 5, 1994 | Issued |
Array
(
[id] => 3117423
[patent_doc_number] => 05465069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-07
[patent_title] => 'Interface circuit and voltage-raising circuit including such a circuit'
[patent_app_type] => 1
[patent_app_number] => 8/269808
[patent_app_country] => US
[patent_app_date] => 1994-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2491
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/465/05465069.pdf
[firstpage_image] =>[orig_patent_app_number] => 269808
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269808 | Interface circuit and voltage-raising circuit including such a circuit | Jun 29, 1994 | Issued |
Array
(
[id] => 3577293
[patent_doc_number] => 05539350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Common mode logic line driver switching stage'
[patent_app_type] => 1
[patent_app_number] => 8/267810
[patent_app_country] => US
[patent_app_date] => 1994-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3518
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 378
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/539/05539350.pdf
[firstpage_image] =>[orig_patent_app_number] => 267810
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/267810 | Common mode logic line driver switching stage | Jun 27, 1994 | Issued |
Array
(
[id] => 3448241
[patent_doc_number] => 05467041
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Variable delay buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/264617
[patent_app_country] => US
[patent_app_date] => 1994-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3805
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467041.pdf
[firstpage_image] =>[orig_patent_app_number] => 264617
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/264617 | Variable delay buffer circuit | Jun 22, 1994 | Issued |