Search

Eunja Adolphe

Examiner (ID: 7947)

Most Active Art Unit
2816
Art Unit(s)
2504, 2816
Total Applications
291
Issued Applications
234
Pending Applications
14
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4005407 [patent_doc_number] => 05986485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Auto-lock circuit guaranteeing low jitter in phase-locked loop frequency synthesizers irrespective of process variations' [patent_app_type] => 1 [patent_app_number] => 8/917483 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4817 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986485.pdf [firstpage_image] =>[orig_patent_app_number] => 917483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917483
Auto-lock circuit guaranteeing low jitter in phase-locked loop frequency synthesizers irrespective of process variations Aug 25, 1997 Issued
Array ( [id] => 3804114 [patent_doc_number] => 05828257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Precision time interval division with digital phase delay lines' [patent_app_type] => 1 [patent_app_number] => 8/915306 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3299 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828257.pdf [firstpage_image] =>[orig_patent_app_number] => 915306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915306
Precision time interval division with digital phase delay lines Aug 18, 1997 Issued
Array ( [id] => 3987155 [patent_doc_number] => 05949268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Variable delay circuit for varying delay time and pulse width' [patent_app_type] => 1 [patent_app_number] => 8/914803 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 70 [patent_no_of_words] => 18784 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949268.pdf [firstpage_image] =>[orig_patent_app_number] => 914803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914803
Variable delay circuit for varying delay time and pulse width Aug 14, 1997 Issued
Array ( [id] => 3950510 [patent_doc_number] => 05982214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Variable delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/905774 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2674 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982214.pdf [firstpage_image] =>[orig_patent_app_number] => 905774 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905774
Variable delay circuit Aug 3, 1997 Issued
Array ( [id] => 4004708 [patent_doc_number] => 05923197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Pulse stuffing circuit for programmable delay line' [patent_app_type] => 1 [patent_app_number] => 8/905066 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3127 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923197.pdf [firstpage_image] =>[orig_patent_app_number] => 905066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905066
Pulse stuffing circuit for programmable delay line Jul 30, 1997 Issued
Array ( [id] => 3955914 [patent_doc_number] => 05999037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Circuit for operating a control transistor from a fusible link' [patent_app_type] => 1 [patent_app_number] => 8/904397 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2866 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999037.pdf [firstpage_image] =>[orig_patent_app_number] => 904397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904397
Circuit for operating a control transistor from a fusible link Jul 30, 1997 Issued
Array ( [id] => 3943137 [patent_doc_number] => 05929681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Delay circuit applied to semiconductor memory device having auto power-down function' [patent_app_type] => 1 [patent_app_number] => 8/902273 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8173 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929681.pdf [firstpage_image] =>[orig_patent_app_number] => 902273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902273
Delay circuit applied to semiconductor memory device having auto power-down function Jul 28, 1997 Issued
Array ( [id] => 3963492 [patent_doc_number] => 05936451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Delay circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/897187 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2993 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936451.pdf [firstpage_image] =>[orig_patent_app_number] => 897187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897187
Delay circuit and method Jul 20, 1997 Issued
Array ( [id] => 4000876 [patent_doc_number] => 05920221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'RC delay circuit for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/892216 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3102 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920221.pdf [firstpage_image] =>[orig_patent_app_number] => 892216 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892216
RC delay circuit for integrated circuits Jul 13, 1997 Issued
Array ( [id] => 4105019 [patent_doc_number] => 06049237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Voltage/current converting circuit and PLL circuit including this circuit' [patent_app_type] => 1 [patent_app_number] => 8/891559 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3791 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049237.pdf [firstpage_image] =>[orig_patent_app_number] => 891559 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891559
Voltage/current converting circuit and PLL circuit including this circuit Jul 10, 1997 Issued
Array ( [id] => 3956852 [patent_doc_number] => 05977801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Self-resetting phase/frequency detector with reduced dead zone' [patent_app_type] => 1 [patent_app_number] => 8/888797 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5153 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977801.pdf [firstpage_image] =>[orig_patent_app_number] => 888797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888797
Self-resetting phase/frequency detector with reduced dead zone Jul 6, 1997 Issued
Array ( [id] => 4092542 [patent_doc_number] => 06025745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Auto-calibrating digital delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/881436 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3724 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025745.pdf [firstpage_image] =>[orig_patent_app_number] => 881436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881436
Auto-calibrating digital delay circuit Jun 23, 1997 Issued
Array ( [id] => 4019682 [patent_doc_number] => 05963074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Programmable delay circuit having calibratable delays' [patent_app_type] => 1 [patent_app_number] => 8/877923 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963074.pdf [firstpage_image] =>[orig_patent_app_number] => 877923 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877923
Programmable delay circuit having calibratable delays Jun 17, 1997 Issued
Array ( [id] => 3931539 [patent_doc_number] => 05945863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Analog delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/878162 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1769 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945863.pdf [firstpage_image] =>[orig_patent_app_number] => 878162 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878162
Analog delay circuit Jun 17, 1997 Issued
Array ( [id] => 3972107 [patent_doc_number] => 05937023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method and circuit for detecting small variations in capacity via delay accumulation' [patent_app_type] => 1 [patent_app_number] => 8/870304 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937023.pdf [firstpage_image] =>[orig_patent_app_number] => 870304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870304
Method and circuit for detecting small variations in capacity via delay accumulation Jun 4, 1997 Issued
Array ( [id] => 3847398 [patent_doc_number] => 05847590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Delay device and delay time measurement device using a ring oscillator' [patent_app_type] => 1 [patent_app_number] => 8/868585 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7602 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847590.pdf [firstpage_image] =>[orig_patent_app_number] => 868585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868585
Delay device and delay time measurement device using a ring oscillator Jun 3, 1997 Issued
Array ( [id] => 3884855 [patent_doc_number] => 05805009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method for operating an electrostatic discharge protection circuit' [patent_app_type] => 1 [patent_app_number] => 8/859693 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2443 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805009.pdf [firstpage_image] =>[orig_patent_app_number] => 859693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859693
Method for operating an electrostatic discharge protection circuit May 20, 1997 Issued
Array ( [id] => 4032543 [patent_doc_number] => 05883538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Low-to-high voltage CMOS driver circuit for driving capacitive loads' [patent_app_type] => 1 [patent_app_number] => 8/861212 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3369 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883538.pdf [firstpage_image] =>[orig_patent_app_number] => 861212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861212
Low-to-high voltage CMOS driver circuit for driving capacitive loads May 20, 1997 Issued
Array ( [id] => 3963317 [patent_doc_number] => 05936439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Switching device with a power FET and an inductive load' [patent_app_type] => 1 [patent_app_number] => 8/855469 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3145 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 540 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936439.pdf [firstpage_image] =>[orig_patent_app_number] => 855469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855469
Switching device with a power FET and an inductive load May 12, 1997 Issued
Array ( [id] => 4069340 [patent_doc_number] => 05896059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Decoupling capacitor fuse system' [patent_app_type] => 1 [patent_app_number] => 8/854224 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1881 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896059.pdf [firstpage_image] =>[orig_patent_app_number] => 854224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854224
Decoupling capacitor fuse system May 8, 1997 Issued
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