
Eunja Adolphe
Examiner (ID: 7947)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2504, 2816 |
| Total Applications | 291 |
| Issued Applications | 234 |
| Pending Applications | 14 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4005407
[patent_doc_number] => 05986485
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Auto-lock circuit guaranteeing low jitter in phase-locked loop frequency synthesizers irrespective of process variations'
[patent_app_type] => 1
[patent_app_number] => 8/917483
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/917483 | Auto-lock circuit guaranteeing low jitter in phase-locked loop frequency synthesizers irrespective of process variations | Aug 25, 1997 | Issued |
Array
(
[id] => 3804114
[patent_doc_number] => 05828257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Precision time interval division with digital phase delay lines'
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[patent_app_number] => 8/915306
[patent_app_country] => US
[patent_app_date] => 1997-08-19
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[pdf_file] => patents/05/828/05828257.pdf
[firstpage_image] =>[orig_patent_app_number] => 915306
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/915306 | Precision time interval division with digital phase delay lines | Aug 18, 1997 | Issued |
Array
(
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[patent_doc_number] => 05949268
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[patent_issue_date] => 1999-09-07
[patent_title] => 'Variable delay circuit for varying delay time and pulse width'
[patent_app_type] => 1
[patent_app_number] => 8/914803
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[patent_app_date] => 1997-08-15
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Array
(
[id] => 3950510
[patent_doc_number] => 05982214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Variable delay circuit'
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Array
(
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[patent_doc_number] => 05923197
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[patent_issue_date] => 1999-07-13
[patent_title] => 'Pulse stuffing circuit for programmable delay line'
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Array
(
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[patent_issue_date] => 1999-12-07
[patent_title] => 'Circuit for operating a control transistor from a fusible link'
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Array
(
[id] => 3943137
[patent_doc_number] => 05929681
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[patent_issue_date] => 1999-07-27
[patent_title] => 'Delay circuit applied to semiconductor memory device having auto power-down function'
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[pdf_file] => patents/05/929/05929681.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902273 | Delay circuit applied to semiconductor memory device having auto power-down function | Jul 28, 1997 | Issued |
Array
(
[id] => 3963492
[patent_doc_number] => 05936451
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[patent_issue_date] => 1999-08-10
[patent_title] => 'Delay circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/897187
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897187 | Delay circuit and method | Jul 20, 1997 | Issued |
Array
(
[id] => 4000876
[patent_doc_number] => 05920221
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'RC delay circuit for integrated circuits'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 892216
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892216 | RC delay circuit for integrated circuits | Jul 13, 1997 | Issued |
Array
(
[id] => 4105019
[patent_doc_number] => 06049237
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[patent_issue_date] => 2000-04-11
[patent_title] => 'Voltage/current converting circuit and PLL circuit including this circuit'
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[firstpage_image] =>[orig_patent_app_number] => 891559
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Array
(
[id] => 3956852
[patent_doc_number] => 05977801
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[patent_issue_date] => 1999-11-02
[patent_title] => 'Self-resetting phase/frequency detector with reduced dead zone'
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Array
(
[id] => 4092542
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[patent_title] => 'Auto-calibrating digital delay circuit'
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Array
(
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Array
(
[id] => 3931539
[patent_doc_number] => 05945863
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[patent_title] => 'Analog delay circuit'
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Array
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Array
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854224 | Decoupling capacitor fuse system | May 8, 1997 | Issued |