
Eunja Adolphe
Examiner (ID: 7947)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2504, 2816 |
| Total Applications | 291 |
| Issued Applications | 234 |
| Pending Applications | 14 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4189460
[patent_doc_number] => 06020775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Adjustable timer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/854290
[patent_app_country] => US
[patent_app_date] => 1997-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6326
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/020/06020775.pdf
[firstpage_image] =>[orig_patent_app_number] => 854290
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854290 | Adjustable timer circuit | May 8, 1997 | Issued |
Array
(
[id] => 4058480
[patent_doc_number] => 05969557
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Delay circuit, oscillation circuit and semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/845836
[patent_app_country] => US
[patent_app_date] => 1997-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 89
[patent_no_of_words] => 24261
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/969/05969557.pdf
[firstpage_image] =>[orig_patent_app_number] => 845836
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/845836 | Delay circuit, oscillation circuit and semiconductor memory device | Apr 27, 1997 | Issued |
Array
(
[id] => 3920061
[patent_doc_number] => 06002280
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Adaptable output phase delay compensation circuit and method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/842441
[patent_app_country] => US
[patent_app_date] => 1997-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2629
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/002/06002280.pdf
[firstpage_image] =>[orig_patent_app_number] => 842441
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/842441 | Adaptable output phase delay compensation circuit and method thereof | Apr 23, 1997 | Issued |
Array
(
[id] => 3982119
[patent_doc_number] => 05905395
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Miller effect-based delay circuit'
[patent_app_type] => 1
[patent_app_number] => 8/837858
[patent_app_country] => US
[patent_app_date] => 1997-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2906
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905395.pdf
[firstpage_image] =>[orig_patent_app_number] => 837858
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837858 | Miller effect-based delay circuit | Apr 21, 1997 | Issued |
Array
(
[id] => 3982162
[patent_doc_number] => 05905398
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Capacitor array having user-adjustable, manufacturer-trimmable capacitance and method'
[patent_app_type] => 1
[patent_app_number] => 8/827725
[patent_app_country] => US
[patent_app_date] => 1997-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4952
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905398.pdf
[firstpage_image] =>[orig_patent_app_number] => 827725
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/827725 | Capacitor array having user-adjustable, manufacturer-trimmable capacitance and method | Apr 7, 1997 | Issued |
Array
(
[id] => 4000783
[patent_doc_number] => 05920216
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Method and system for generating digital clock signals of programmable frequency employing programmable delay lines'
[patent_app_type] => 1
[patent_app_number] => 8/826586
[patent_app_country] => US
[patent_app_date] => 1997-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4625
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920216.pdf
[firstpage_image] =>[orig_patent_app_number] => 826586
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/826586 | Method and system for generating digital clock signals of programmable frequency employing programmable delay lines | Apr 2, 1997 | Issued |
Array
(
[id] => 4004696
[patent_doc_number] => 05923196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Band-selectable phase-locked loop'
[patent_app_type] => 1
[patent_app_number] => 8/829176
[patent_app_country] => US
[patent_app_date] => 1997-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5416
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923196.pdf
[firstpage_image] =>[orig_patent_app_number] => 829176
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/829176 | Band-selectable phase-locked loop | Mar 30, 1997 | Issued |
Array
(
[id] => 4005504
[patent_doc_number] => 05986492
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Delay element for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/829746
[patent_app_country] => US
[patent_app_date] => 1997-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1155
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/986/05986492.pdf
[firstpage_image] =>[orig_patent_app_number] => 829746
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/829746 | Delay element for integrated circuits | Mar 30, 1997 | Issued |
Array
(
[id] => 4050469
[patent_doc_number] => 05912573
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Synchronizing clock pulse generator for logic derived clock signals for a programmable device'
[patent_app_type] => 1
[patent_app_number] => 8/828325
[patent_app_country] => US
[patent_app_date] => 1997-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7683
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/912/05912573.pdf
[firstpage_image] =>[orig_patent_app_number] => 828325
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/828325 | Synchronizing clock pulse generator for logic derived clock signals for a programmable device | Mar 27, 1997 | Issued |
Array
(
[id] => 4160913
[patent_doc_number] => 06124752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-26
[patent_title] => 'Semiconductor integrated circuit device controlling the threshold value thereof for power reduction at standby mode'
[patent_app_type] => 1
[patent_app_number] => 8/825272
[patent_app_country] => US
[patent_app_date] => 1997-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 27
[patent_no_of_words] => 9242
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/124/06124752.pdf
[firstpage_image] =>[orig_patent_app_number] => 825272
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/825272 | Semiconductor integrated circuit device controlling the threshold value thereof for power reduction at standby mode | Mar 26, 1997 | Issued |
Array
(
[id] => 3847660
[patent_doc_number] => 05744992
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Digital phase shifter'
[patent_app_type] => 1
[patent_app_number] => 8/823591
[patent_app_country] => US
[patent_app_date] => 1997-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4031
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/744/05744992.pdf
[firstpage_image] =>[orig_patent_app_number] => 823591
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/823591 | Digital phase shifter | Mar 24, 1997 | Issued |
| 08/737249 | VARIABLE DELAY CIRCUIT AND TIMING SIGNAL GENERATION CIRCUIT | Mar 2, 1997 | Abandoned |
Array
(
[id] => 4092879
[patent_doc_number] => 06018261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Method and apparatus for providing a low voltage level shift'
[patent_app_type] => 1
[patent_app_number] => 8/801665
[patent_app_country] => US
[patent_app_date] => 1997-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5002
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018261.pdf
[firstpage_image] =>[orig_patent_app_number] => 801665
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/801665 | Method and apparatus for providing a low voltage level shift | Feb 17, 1997 | Issued |
Array
(
[id] => 4082026
[patent_doc_number] => 05966037
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Method for manufacturing an integrated circuit with programmable non-overlapping-clock-edge capability'
[patent_app_type] => 1
[patent_app_number] => 8/795363
[patent_app_country] => US
[patent_app_date] => 1997-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 4279
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/966/05966037.pdf
[firstpage_image] =>[orig_patent_app_number] => 795363
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/795363 | Method for manufacturing an integrated circuit with programmable non-overlapping-clock-edge capability | Feb 3, 1997 | Issued |
Array
(
[id] => 4029005
[patent_doc_number] => 05926046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Semiconductor integrated circuit employing smaller number of elements to provide phase-locked clock signal'
[patent_app_type] => 1
[patent_app_number] => 8/794499
[patent_app_country] => US
[patent_app_date] => 1997-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 42
[patent_no_of_words] => 12310
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926046.pdf
[firstpage_image] =>[orig_patent_app_number] => 794499
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/794499 | Semiconductor integrated circuit employing smaller number of elements to provide phase-locked clock signal | Feb 3, 1997 | Issued |
Array
(
[id] => 4040650
[patent_doc_number] => 05994933
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Semiconductor device for controlling a delay time of an output signal of a PLL'
[patent_app_type] => 1
[patent_app_number] => 8/790016
[patent_app_country] => US
[patent_app_date] => 1997-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 5245
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994933.pdf
[firstpage_image] =>[orig_patent_app_number] => 790016
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/790016 | Semiconductor device for controlling a delay time of an output signal of a PLL | Jan 27, 1997 | Issued |
Array
(
[id] => 3987166
[patent_doc_number] => 05949269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Method and apparatus to reduce signal delay mismatch in a high speed interface'
[patent_app_type] => 1
[patent_app_number] => 8/782601
[patent_app_country] => US
[patent_app_date] => 1997-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3820
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/949/05949269.pdf
[firstpage_image] =>[orig_patent_app_number] => 782601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/782601 | Method and apparatus to reduce signal delay mismatch in a high speed interface | Jan 12, 1997 | Issued |
Array
(
[id] => 4050540
[patent_doc_number] => 05912578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Multiplexer circuit having diode bridge switches'
[patent_app_type] => 1
[patent_app_number] => 8/781573
[patent_app_country] => US
[patent_app_date] => 1997-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5888
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 323
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/912/05912578.pdf
[firstpage_image] =>[orig_patent_app_number] => 781573
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/781573 | Multiplexer circuit having diode bridge switches | Jan 8, 1997 | Issued |
| 08/778416 | STRUCTURE AND DEVICE FOR SELECTING DESIGN OPTIONS IN AN INTEGRATED CIRCUIT | Dec 30, 1996 | Abandoned |
Array
(
[id] => 3982639
[patent_doc_number] => 05917357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Delay circuit providing constant delay regardless of variations in power supply'
[patent_app_type] => 1
[patent_app_number] => 8/773603
[patent_app_country] => US
[patent_app_date] => 1996-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1723
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917357.pdf
[firstpage_image] =>[orig_patent_app_number] => 773603
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/773603 | Delay circuit providing constant delay regardless of variations in power supply | Dec 26, 1996 | Issued |