
Eunja Adolphe
Examiner (ID: 7947)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2504, 2816 |
| Total Applications | 291 |
| Issued Applications | 234 |
| Pending Applications | 14 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4011445
[patent_doc_number] => 05859554
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Variable delay circuit'
[patent_app_type] => 1
[patent_app_number] => 8/773234
[patent_app_country] => US
[patent_app_date] => 1996-12-23
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Array
(
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[patent_issue_date] => 1997-08-12
[patent_title] => 'Master-slave flip-flop circuit with bypass'
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[patent_app_number] => 8/768792
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 05923199
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[patent_issue_date] => 1999-07-13
[patent_title] => 'Delay circuit for giving delays of variable width'
[patent_app_type] => 1
[patent_app_number] => 8/769726
[patent_app_country] => US
[patent_app_date] => 1996-12-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/769726 | Delay circuit for giving delays of variable width | Dec 17, 1996 | Issued |
Array
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[patent_issue_date] => 1998-09-01
[patent_title] => 'Circuit and method for generating a delayed output signal'
[patent_app_type] => 1
[patent_app_number] => 8/768903
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[patent_app_date] => 1996-12-17
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Array
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[patent_issue_date] => 1999-12-14
[patent_title] => 'Feedback apparatus for adjusting clock delay'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/771340 | Feedback apparatus for adjusting clock delay | Dec 15, 1996 | Issued |
Array
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[patent_issue_date] => 1999-09-14
[patent_title] => 'Circuit and method for generating non-overlapping clock signals for an integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762169 | Circuit and method for generating non-overlapping clock signals for an integrated circuit | Dec 8, 1996 | Issued |
Array
(
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[patent_issue_date] => 1999-06-15
[patent_title] => 'Dual loop PLL with secondary loop to achieve 50% duty cycle'
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Array
(
[id] => 4000691
[patent_doc_number] => 05920210
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[patent_issue_date] => 1999-07-06
[patent_title] => 'Inverter-controlled digital interface circuit with dual switching points for increased speed'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754755 | Inverter-controlled digital interface circuit with dual switching points for increased speed | Nov 20, 1996 | Issued |
Array
(
[id] => 3747016
[patent_doc_number] => 05754070
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[patent_issue_date] => 1998-05-19
[patent_title] => 'Metastableproof flip-flop'
[patent_app_type] => 1
[patent_app_number] => 8/754507
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754507 | Metastableproof flip-flop | Nov 18, 1996 | Issued |
Array
(
[id] => 3934690
[patent_doc_number] => 05877642
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[patent_issue_date] => 1999-03-02
[patent_title] => 'Latch circuit for receiving small amplitude signals'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/751612 | Latch circuit for receiving small amplitude signals | Nov 17, 1996 | Issued |
Array
(
[id] => 4019667
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[patent_issue_date] => 1999-10-05
[patent_title] => '.pi./2 phase shifter'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/751730 | .pi./2 phase shifter | Nov 17, 1996 | Issued |
Array
(
[id] => 3734388
[patent_doc_number] => 05670905
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[patent_title] => 'Low-to-high voltage CMOS driver circuit for driving capacitive loads'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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