Search

Eunja Adolphe

Examiner (ID: 7947)

Most Active Art Unit
2816
Art Unit(s)
2504, 2816
Total Applications
291
Issued Applications
234
Pending Applications
14
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4011445 [patent_doc_number] => 05859554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Variable delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/773234 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859554.pdf [firstpage_image] =>[orig_patent_app_number] => 773234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773234
Variable delay circuit Dec 22, 1996 Issued
Array ( [id] => 3666838 [patent_doc_number] => 05656962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Master-slave flip-flop circuit with bypass' [patent_app_type] => 1 [patent_app_number] => 8/768792 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4807 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656962.pdf [firstpage_image] =>[orig_patent_app_number] => 768792 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768792
Master-slave flip-flop circuit with bypass Dec 17, 1996 Issued
Array ( [id] => 4004736 [patent_doc_number] => 05923199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Delay circuit for giving delays of variable width' [patent_app_type] => 1 [patent_app_number] => 8/769726 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3462 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923199.pdf [firstpage_image] =>[orig_patent_app_number] => 769726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769726
Delay circuit for giving delays of variable width Dec 17, 1996 Issued
Array ( [id] => 3750232 [patent_doc_number] => 05801567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Circuit and method for generating a delayed output signal' [patent_app_type] => 1 [patent_app_number] => 8/768903 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2148 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801567.pdf [firstpage_image] =>[orig_patent_app_number] => 768903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768903
Circuit and method for generating a delayed output signal Dec 16, 1996 Issued
Array ( [id] => 3920088 [patent_doc_number] => 06002282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Feedback apparatus for adjusting clock delay' [patent_app_type] => 1 [patent_app_number] => 8/771340 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5146 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002282.pdf [firstpage_image] =>[orig_patent_app_number] => 771340 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/771340
Feedback apparatus for adjusting clock delay Dec 15, 1996 Issued
Array ( [id] => 3934228 [patent_doc_number] => 05952863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Circuit and method for generating non-overlapping clock signals for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/762169 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952863.pdf [firstpage_image] =>[orig_patent_app_number] => 762169 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762169
Circuit and method for generating non-overlapping clock signals for an integrated circuit Dec 8, 1996 Issued
Array ( [id] => 4050483 [patent_doc_number] => 05912574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Dual loop PLL with secondary loop to achieve 50% duty cycle' [patent_app_type] => 1 [patent_app_number] => 8/762154 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 3895 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912574.pdf [firstpage_image] =>[orig_patent_app_number] => 762154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762154
Dual loop PLL with secondary loop to achieve 50% duty cycle Dec 8, 1996 Issued
Array ( [id] => 4000691 [patent_doc_number] => 05920210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Inverter-controlled digital interface circuit with dual switching points for increased speed' [patent_app_type] => 1 [patent_app_number] => 8/754755 [patent_app_country] => US [patent_app_date] => 1996-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4397 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920210.pdf [firstpage_image] =>[orig_patent_app_number] => 754755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754755
Inverter-controlled digital interface circuit with dual switching points for increased speed Nov 20, 1996 Issued
Array ( [id] => 3747016 [patent_doc_number] => 05754070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Metastableproof flip-flop' [patent_app_type] => 1 [patent_app_number] => 8/754507 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2802 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754070.pdf [firstpage_image] =>[orig_patent_app_number] => 754507 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754507
Metastableproof flip-flop Nov 18, 1996 Issued
Array ( [id] => 3934690 [patent_doc_number] => 05877642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Latch circuit for receiving small amplitude signals' [patent_app_type] => 1 [patent_app_number] => 8/751612 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4346 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877642.pdf [firstpage_image] =>[orig_patent_app_number] => 751612 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751612
Latch circuit for receiving small amplitude signals Nov 17, 1996 Issued
Array ( [id] => 4019667 [patent_doc_number] => 05963073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => '.pi./2 phase shifter' [patent_app_type] => 1 [patent_app_number] => 8/751730 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 4909 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963073.pdf [firstpage_image] =>[orig_patent_app_number] => 751730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751730
.pi./2 phase shifter Nov 17, 1996 Issued
Array ( [id] => 3734388 [patent_doc_number] => 05670905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Low-to-high voltage CMOS driver circuit for driving capacitive loads' [patent_app_type] => 1 [patent_app_number] => 8/749899 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3365 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670905.pdf [firstpage_image] =>[orig_patent_app_number] => 749899 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/749899
Low-to-high voltage CMOS driver circuit for driving capacitive loads Nov 12, 1996 Issued
Array ( [id] => 3799251 [patent_doc_number] => 05726598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Semiconductor device having voltage sensing element' [patent_app_type] => 1 [patent_app_number] => 8/743567 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7085 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726598.pdf [firstpage_image] =>[orig_patent_app_number] => 743567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743567
Semiconductor device having voltage sensing element Nov 3, 1996 Issued
Array ( [id] => 3867130 [patent_doc_number] => 05793238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'RC delay with feedback' [patent_app_type] => 1 [patent_app_number] => 8/743005 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2324 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793238.pdf [firstpage_image] =>[orig_patent_app_number] => 743005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743005
RC delay with feedback Oct 31, 1996 Issued
Array ( [id] => 3814616 [patent_doc_number] => 05831462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Conditional latching mechanism and pipelined microprocessor employing the same' [patent_app_type] => 1 [patent_app_number] => 8/744707 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3700 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831462.pdf [firstpage_image] =>[orig_patent_app_number] => 744707 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744707
Conditional latching mechanism and pipelined microprocessor employing the same Oct 30, 1996 Issued
Array ( [id] => 3934598 [patent_doc_number] => 05877636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Synchronous multiplexer for clock signals' [patent_app_type] => 1 [patent_app_number] => 8/733885 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4088 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877636.pdf [firstpage_image] =>[orig_patent_app_number] => 733885 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733885
Synchronous multiplexer for clock signals Oct 17, 1996 Issued
Array ( [id] => 4021499 [patent_doc_number] => 05880612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Signal de-skewing using programmable dual delay-locked loop' [patent_app_type] => 1 [patent_app_number] => 8/733617 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5259 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880612.pdf [firstpage_image] =>[orig_patent_app_number] => 733617 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733617
Signal de-skewing using programmable dual delay-locked loop Oct 16, 1996 Issued
Array ( [id] => 3767496 [patent_doc_number] => 05852380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Phase adjusting circuit, system including the same and phase adjusting method' [patent_app_type] => 1 [patent_app_number] => 8/731437 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 11911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852380.pdf [firstpage_image] =>[orig_patent_app_number] => 731437 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731437
Phase adjusting circuit, system including the same and phase adjusting method Oct 14, 1996 Issued
Array ( [id] => 3867852 [patent_doc_number] => 05796288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/730170 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4447 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796288.pdf [firstpage_image] =>[orig_patent_app_number] => 730170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730170
Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor Oct 14, 1996 Issued
Array ( [id] => 3867764 [patent_doc_number] => 05796283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'BINMOS latch circuit with symmetric set-up times' [patent_app_type] => 1 [patent_app_number] => 8/731621 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1885 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796283.pdf [firstpage_image] =>[orig_patent_app_number] => 731621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731621
BINMOS latch circuit with symmetric set-up times Oct 14, 1996 Issued
Menu