Search

Eunja Adolphe

Examiner (ID: 7947)

Most Active Art Unit
2816
Art Unit(s)
2504, 2816
Total Applications
291
Issued Applications
234
Pending Applications
14
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3941356 [patent_doc_number] => 05939924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Integrating circuit having high time constant, low bandwidth feedback loop arrangements' [patent_app_type] => 1 [patent_app_number] => 8/729099 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2953 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939924.pdf [firstpage_image] =>[orig_patent_app_number] => 729099 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729099
Integrating circuit having high time constant, low bandwidth feedback loop arrangements Oct 10, 1996 Issued
Array ( [id] => 3750346 [patent_doc_number] => 05801574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Charge sharing detection circuit for anti-fuses' [patent_app_type] => 1 [patent_app_number] => 8/727797 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3821 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801574.pdf [firstpage_image] =>[orig_patent_app_number] => 727797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727797
Charge sharing detection circuit for anti-fuses Oct 6, 1996 Issued
Array ( [id] => 3791319 [patent_doc_number] => 05821787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Power-on reset circuit with well-defined reassertion voltage' [patent_app_type] => 1 [patent_app_number] => 8/726461 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5695 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821787.pdf [firstpage_image] =>[orig_patent_app_number] => 726461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/726461
Power-on reset circuit with well-defined reassertion voltage Oct 3, 1996 Issued
Array ( [id] => 3777777 [patent_doc_number] => 05773997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Reference circuit for sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/727842 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3528 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773997.pdf [firstpage_image] =>[orig_patent_app_number] => 727842 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727842
Reference circuit for sense amplifier Oct 3, 1996 Issued
Array ( [id] => 4040694 [patent_doc_number] => 05942926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'PLL circuit' [patent_app_type] => 1 [patent_app_number] => 8/721959 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8202 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/942/05942926.pdf [firstpage_image] =>[orig_patent_app_number] => 721959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721959
PLL circuit Sep 26, 1996 Issued
Array ( [id] => 4000105 [patent_doc_number] => 05892383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Parallel voltage controlled resistance elements' [patent_app_type] => 1 [patent_app_number] => 8/718646 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4440 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892383.pdf [firstpage_image] =>[orig_patent_app_number] => 718646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718646
Parallel voltage controlled resistance elements Sep 26, 1996 Issued
Array ( [id] => 3801640 [patent_doc_number] => 05781056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Variable delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/721058 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3712 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781056.pdf [firstpage_image] =>[orig_patent_app_number] => 721058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721058
Variable delay circuit Sep 25, 1996 Issued
Array ( [id] => 3859853 [patent_doc_number] => 05767716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Noise insensitive high performance energy efficient push pull isolation flip-flop circuits' [patent_app_type] => 1 [patent_app_number] => 8/720165 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4231 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767716.pdf [firstpage_image] =>[orig_patent_app_number] => 720165 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720165
Noise insensitive high performance energy efficient push pull isolation flip-flop circuits Sep 24, 1996 Issued
Array ( [id] => 3823282 [patent_doc_number] => 05789966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Distributed multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/715654 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2935 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789966.pdf [firstpage_image] =>[orig_patent_app_number] => 715654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/715654
Distributed multiplexer Sep 17, 1996 Issued
Array ( [id] => 3876483 [patent_doc_number] => 05838180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Low-voltage frequency synthesizer' [patent_app_type] => 1 [patent_app_number] => 8/713051 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2631 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838180.pdf [firstpage_image] =>[orig_patent_app_number] => 713051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713051
Low-voltage frequency synthesizer Sep 11, 1996 Issued
Array ( [id] => 3982208 [patent_doc_number] => 05905401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice' [patent_app_type] => 1 [patent_app_number] => 8/711127 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3259 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905401.pdf [firstpage_image] =>[orig_patent_app_number] => 711127 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711127
Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice Sep 8, 1996 Issued
Array ( [id] => 3847548 [patent_doc_number] => 05744983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Phase detector with edge-sensitive enable and disable' [patent_app_type] => 1 [patent_app_number] => 8/702287 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8500 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744983.pdf [firstpage_image] =>[orig_patent_app_number] => 702287 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702287
Phase detector with edge-sensitive enable and disable Aug 22, 1996 Issued
Array ( [id] => 3801595 [patent_doc_number] => 05781053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Positive edge triggered flip flop' [patent_app_type] => 1 [patent_app_number] => 8/701016 [patent_app_country] => US [patent_app_date] => 1996-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 3758 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781053.pdf [firstpage_image] =>[orig_patent_app_number] => 701016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701016
Positive edge triggered flip flop Aug 20, 1996 Issued
Array ( [id] => 3818136 [patent_doc_number] => 05812013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method and apparatus for calibrating integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/697192 [patent_app_country] => US [patent_app_date] => 1996-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3171 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812013.pdf [firstpage_image] =>[orig_patent_app_number] => 697192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/697192
Method and apparatus for calibrating integrated circuits Aug 20, 1996 Issued
08/699850 QUARTER-SQUARE MULTIPLIER BASED ON THE DYNAMIC BIAS CURRENT TECHNIQUE Aug 19, 1996 Abandoned
Array ( [id] => 3694273 [patent_doc_number] => 05663667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Switched leading edge replacement for current sense signal' [patent_app_type] => 1 [patent_app_number] => 8/697038 [patent_app_country] => US [patent_app_date] => 1996-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2803 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663667.pdf [firstpage_image] =>[orig_patent_app_number] => 697038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/697038
Switched leading edge replacement for current sense signal Aug 18, 1996 Issued
Array ( [id] => 3750360 [patent_doc_number] => 05801575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Process and device controlling the operation of a portable electronic object supplied via its antenna' [patent_app_type] => 1 [patent_app_number] => 8/696959 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3536 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801575.pdf [firstpage_image] =>[orig_patent_app_number] => 696959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696959
Process and device controlling the operation of a portable electronic object supplied via its antenna Aug 15, 1996 Issued
08/696528 D-TYPE LATCH CIRCUIT AND DEVICE USING THE SAME Aug 13, 1996 Abandoned
Array ( [id] => 3791398 [patent_doc_number] => 05821793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Variable delay circuit and a variable pulse width circuit' [patent_app_type] => 1 [patent_app_number] => 8/695575 [patent_app_country] => US [patent_app_date] => 1996-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 6096 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821793.pdf [firstpage_image] =>[orig_patent_app_number] => 695575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/695575
Variable delay circuit and a variable pulse width circuit Aug 11, 1996 Issued
Array ( [id] => 3817887 [patent_doc_number] => 05811995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Circuit for switching between different frequency clock domains that are out of phase' [patent_app_type] => 1 [patent_app_number] => 8/691832 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6769 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811995.pdf [firstpage_image] =>[orig_patent_app_number] => 691832 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691832
Circuit for switching between different frequency clock domains that are out of phase Aug 1, 1996 Issued
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