Search

Eunja Adolphe

Examiner (ID: 7947)

Most Active Art Unit
2816
Art Unit(s)
2504, 2816
Total Applications
291
Issued Applications
234
Pending Applications
14
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3818026 [patent_doc_number] => 05812005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Auto zero circuitry and associated method' [patent_app_type] => 1 [patent_app_number] => 8/688589 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2519 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812005.pdf [firstpage_image] =>[orig_patent_app_number] => 688589 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/688589
Auto zero circuitry and associated method Jul 29, 1996 Issued
Array ( [id] => 3859910 [patent_doc_number] => 05767720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Clock signal supplying circuit' [patent_app_type] => 1 [patent_app_number] => 8/686041 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 1 [patent_no_of_words] => 4387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767720.pdf [firstpage_image] =>[orig_patent_app_number] => 686041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686041
Clock signal supplying circuit Jul 24, 1996 Issued
Array ( [id] => 3812994 [patent_doc_number] => 05854563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Process control monitoring system and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/684964 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4024 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854563.pdf [firstpage_image] =>[orig_patent_app_number] => 684964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684964
Process control monitoring system and method therefor Jul 18, 1996 Issued
Array ( [id] => 3784935 [patent_doc_number] => 05818289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit' [patent_app_type] => 1 [patent_app_number] => 8/683474 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7864 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818289.pdf [firstpage_image] =>[orig_patent_app_number] => 683474 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/683474
Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit Jul 17, 1996 Issued
Array ( [id] => 3859895 [patent_doc_number] => 05767719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Delay circuit using capacitor and transistor' [patent_app_type] => 1 [patent_app_number] => 8/680975 [patent_app_country] => US [patent_app_date] => 1996-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2802 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767719.pdf [firstpage_image] =>[orig_patent_app_number] => 680975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680975
Delay circuit using capacitor and transistor Jul 15, 1996 Issued
08/677754 PHASE COMPARATOR Jul 9, 1996 Abandoned
Array ( [id] => 3955804 [patent_doc_number] => 05999029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Meta-hardened flip-flop' [patent_app_type] => 1 [patent_app_number] => 8/671862 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3105 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999029.pdf [firstpage_image] =>[orig_patent_app_number] => 671862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671862
Meta-hardened flip-flop Jun 27, 1996 Issued
Array ( [id] => 3953066 [patent_doc_number] => 05990716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method and system for recovering digital data from a transmitted balanced signal' [patent_app_type] => 1 [patent_app_number] => 8/672180 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3407 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990716.pdf [firstpage_image] =>[orig_patent_app_number] => 672180 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672180
Method and system for recovering digital data from a transmitted balanced signal Jun 26, 1996 Issued
Array ( [id] => 3784872 [patent_doc_number] => 05818285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Fuse signature circuits for microelectronic devices' [patent_app_type] => 1 [patent_app_number] => 8/668346 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2614 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818285.pdf [firstpage_image] =>[orig_patent_app_number] => 668346 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668346
Fuse signature circuits for microelectronic devices Jun 25, 1996 Issued
Array ( [id] => 3839122 [patent_doc_number] => 05815016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Phase-locked delay loop for clock correction' [patent_app_type] => 1 [patent_app_number] => 8/665169 [patent_app_country] => US [patent_app_date] => 1996-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5795 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815016.pdf [firstpage_image] =>[orig_patent_app_number] => 665169 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665169
Phase-locked delay loop for clock correction Jun 13, 1996 Issued
Array ( [id] => 3747030 [patent_doc_number] => 05754071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Digital signal delaying method and circuit' [patent_app_type] => 1 [patent_app_number] => 8/663772 [patent_app_country] => US [patent_app_date] => 1996-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2783 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754071.pdf [firstpage_image] =>[orig_patent_app_number] => 663772 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663772
Digital signal delaying method and circuit Jun 13, 1996 Issued
Array ( [id] => 3832413 [patent_doc_number] => 05783955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Driver circuit arrangement used in a local area network' [patent_app_type] => 1 [patent_app_number] => 8/657537 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5844 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783955.pdf [firstpage_image] =>[orig_patent_app_number] => 657537 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657537
Driver circuit arrangement used in a local area network Jun 3, 1996 Issued
Array ( [id] => 3801625 [patent_doc_number] => 05781055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Apparatus and method for instantaneous stretching of clock signals in a delay-locked loop multi-phase clock generator' [patent_app_type] => 1 [patent_app_number] => 8/655835 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3689 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781055.pdf [firstpage_image] =>[orig_patent_app_number] => 655835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655835
Apparatus and method for instantaneous stretching of clock signals in a delay-locked loop multi-phase clock generator May 30, 1996 Issued
Array ( [id] => 3920136 [patent_doc_number] => 06002285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Circuitry and method for latching information' [patent_app_type] => 1 [patent_app_number] => 8/654361 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6171 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002285.pdf [firstpage_image] =>[orig_patent_app_number] => 654361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654361
Circuitry and method for latching information May 27, 1996 Issued
Array ( [id] => 3955773 [patent_doc_number] => 05999027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Phase compensating apparatus and delay controlling circuit' [patent_app_type] => 1 [patent_app_number] => 8/654975 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7868 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999027.pdf [firstpage_image] =>[orig_patent_app_number] => 654975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654975
Phase compensating apparatus and delay controlling circuit May 27, 1996 Issued
Array ( [id] => 3747373 [patent_doc_number] => 05786713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Driver circuit and a method for generating a driving signal' [patent_app_type] => 1 [patent_app_number] => 8/651727 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 37 [patent_no_of_words] => 14806 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786713.pdf [firstpage_image] =>[orig_patent_app_number] => 651727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651727
Driver circuit and a method for generating a driving signal May 21, 1996 Issued
Array ( [id] => 3966024 [patent_doc_number] => 05900757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Clock stopping schemes for data buffer' [patent_app_type] => 1 [patent_app_number] => 8/672329 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4841 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900757.pdf [firstpage_image] =>[orig_patent_app_number] => 672329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672329
Clock stopping schemes for data buffer Apr 30, 1996 Issued
Array ( [id] => 3854020 [patent_doc_number] => 05719515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Digital delay line' [patent_app_type] => 1 [patent_app_number] => 8/641003 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3492 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719515.pdf [firstpage_image] =>[orig_patent_app_number] => 641003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641003
Digital delay line Apr 28, 1996 Issued
Array ( [id] => 3894463 [patent_doc_number] => 05777501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Digital delay line for a reduced jitter digital delay lock loop' [patent_app_type] => 1 [patent_app_number] => 8/638809 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2533 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777501.pdf [firstpage_image] =>[orig_patent_app_number] => 638809 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638809
Digital delay line for a reduced jitter digital delay lock loop Apr 28, 1996 Issued
08/638241 FREQUENCY MULTIPLIER Apr 24, 1996 Abandoned
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