
Eunja Adolphe
Examiner (ID: 7947)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2504, 2816 |
| Total Applications | 291 |
| Issued Applications | 234 |
| Pending Applications | 14 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3791361
[patent_doc_number] => 05821790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Power line synchronization conditioner'
[patent_app_type] => 1
[patent_app_number] => 8/637292
[patent_app_country] => US
[patent_app_date] => 1996-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2841
[patent_no_of_claims] => 18
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/821/05821790.pdf
[firstpage_image] =>[orig_patent_app_number] => 637292
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/637292 | Power line synchronization conditioner | Apr 23, 1996 | Issued |
Array
(
[id] => 3837094
[patent_doc_number] => 05760620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks'
[patent_app_type] => 1
[patent_app_number] => 8/635620
[patent_app_country] => US
[patent_app_date] => 1996-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4967
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760620.pdf
[firstpage_image] =>[orig_patent_app_number] => 635620
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/635620 | CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks | Apr 21, 1996 | Issued |
Array
(
[id] => 4015252
[patent_doc_number] => 05889427
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Voltage step-up circuit'
[patent_app_type] => 1
[patent_app_number] => 8/634940
[patent_app_country] => US
[patent_app_date] => 1996-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/889/05889427.pdf
[firstpage_image] =>[orig_patent_app_number] => 634940
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634940 | Voltage step-up circuit | Apr 18, 1996 | Issued |
Array
(
[id] => 3699863
[patent_doc_number] => 05650740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'TTL delay matching circuit'
[patent_app_type] => 1
[patent_app_number] => 8/632206
[patent_app_country] => US
[patent_app_date] => 1996-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2521
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/650/05650740.pdf
[firstpage_image] =>[orig_patent_app_number] => 632206
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632206 | TTL delay matching circuit | Apr 14, 1996 | Issued |
Array
(
[id] => 3653404
[patent_doc_number] => 05629643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Feedback latch and method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/632181
[patent_app_country] => US
[patent_app_date] => 1996-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3384
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/629/05629643.pdf
[firstpage_image] =>[orig_patent_app_number] => 632181
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632181 | Feedback latch and method therefor | Apr 14, 1996 | Issued |
Array
(
[id] => 3707706
[patent_doc_number] => 05646564
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-08
[patent_title] => 'Phase-locked delay loop for clock correction'
[patent_app_type] => 1
[patent_app_number] => 8/632523
[patent_app_country] => US
[patent_app_date] => 1996-04-12
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/646/05646564.pdf
[firstpage_image] =>[orig_patent_app_number] => 632523
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632523 | Phase-locked delay loop for clock correction | Apr 11, 1996 | Issued |
Array
(
[id] => 3782596
[patent_doc_number] => 05808503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Input signal processing circuit'
[patent_app_type] => 1
[patent_app_number] => 8/632039
[patent_app_country] => US
[patent_app_date] => 1996-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808503.pdf
[firstpage_image] =>[orig_patent_app_number] => 632039
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632039 | Input signal processing circuit | Apr 11, 1996 | Issued |
Array
(
[id] => 3796556
[patent_doc_number] => 05841307
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Delay device and delay time measurement device using a ring oscillator'
[patent_app_type] => 1
[patent_app_number] => 8/626957
[patent_app_country] => US
[patent_app_date] => 1996-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7612
[patent_no_of_claims] => 9
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[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841307.pdf
[firstpage_image] =>[orig_patent_app_number] => 626957
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/626957 | Delay device and delay time measurement device using a ring oscillator | Apr 2, 1996 | Issued |
Array
(
[id] => 3885005
[patent_doc_number] => 05748025
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/623969
[patent_app_country] => US
[patent_app_date] => 1996-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 8629
[patent_no_of_claims] => 30
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748025.pdf
[firstpage_image] =>[orig_patent_app_number] => 623969
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/623969 | Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit | Mar 28, 1996 | Issued |
Array
(
[id] => 3853949
[patent_doc_number] => 05719510
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Software configurable digital clock generator'
[patent_app_type] => 1
[patent_app_number] => 8/622375
[patent_app_country] => US
[patent_app_date] => 1996-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5642
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[pdf_file] => patents/05/719/05719510.pdf
[firstpage_image] =>[orig_patent_app_number] => 622375
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/622375 | Software configurable digital clock generator | Mar 26, 1996 | Issued |
Array
(
[id] => 3854006
[patent_doc_number] => 05719514
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Delay circuit compensating for variations in delay time'
[patent_app_type] => 1
[patent_app_number] => 8/621969
[patent_app_country] => US
[patent_app_date] => 1996-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/719/05719514.pdf
[firstpage_image] =>[orig_patent_app_number] => 621969
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/621969 | Delay circuit compensating for variations in delay time | Mar 25, 1996 | Issued |
Array
(
[id] => 3693573
[patent_doc_number] => 05644262
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Digitally controlled capacitive load'
[patent_app_type] => 1
[patent_app_number] => 8/621732
[patent_app_country] => US
[patent_app_date] => 1996-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/05/644/05644262.pdf
[firstpage_image] =>[orig_patent_app_number] => 621732
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/621732 | Digitally controlled capacitive load | Mar 20, 1996 | Issued |
Array
(
[id] => 3629126
[patent_doc_number] => 05602499
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Multistage switching circuit'
[patent_app_type] => 1
[patent_app_number] => 8/619416
[patent_app_country] => US
[patent_app_date] => 1996-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/602/05602499.pdf
[firstpage_image] =>[orig_patent_app_number] => 619416
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/619416 | Multistage switching circuit | Mar 20, 1996 | Issued |
Array
(
[id] => 3823332
[patent_doc_number] => 05789969
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Digital delay circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/617994
[patent_app_country] => US
[patent_app_date] => 1996-03-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/789/05789969.pdf
[firstpage_image] =>[orig_patent_app_number] => 617994
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/617994 | Digital delay circuit and method | Mar 14, 1996 | Issued |
Array
(
[id] => 3722942
[patent_doc_number] => 05617048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Hysteretic power-up circuit'
[patent_app_type] => 1
[patent_app_number] => 8/614911
[patent_app_country] => US
[patent_app_date] => 1996-03-13
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[pdf_file] => patents/05/617/05617048.pdf
[firstpage_image] =>[orig_patent_app_number] => 614911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/614911 | Hysteretic power-up circuit | Mar 12, 1996 | Issued |
Array
(
[id] => 3837192
[patent_doc_number] => 05760627
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Low power CMOS latch'
[patent_app_type] => 1
[patent_app_number] => 8/614123
[patent_app_country] => US
[patent_app_date] => 1996-03-12
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760627.pdf
[firstpage_image] =>[orig_patent_app_number] => 614123
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/614123 | Low power CMOS latch | Mar 11, 1996 | Issued |
Array
(
[id] => 3700792
[patent_doc_number] => 05619161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Diffrential charge pump with integrated common mode control'
[patent_app_type] => 1
[patent_app_number] => 8/611313
[patent_app_country] => US
[patent_app_date] => 1996-03-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/619/05619161.pdf
[firstpage_image] =>[orig_patent_app_number] => 611313
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/611313 | Diffrential charge pump with integrated common mode control | Mar 4, 1996 | Issued |
Array
(
[id] => 3893219
[patent_doc_number] => 05714896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Fractional-N frequency divider system'
[patent_app_type] => 1
[patent_app_number] => 8/608559
[patent_app_country] => US
[patent_app_date] => 1996-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/05/714/05714896.pdf
[firstpage_image] =>[orig_patent_app_number] => 608559
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/608559 | Fractional-N frequency divider system | Feb 27, 1996 | Issued |
| 08/603499 | LOW-TO-HIGH VOLTAGE CMOS DRIVER CIRCUIT FOR DRIVING CAPACITIVE LOADS | Feb 19, 1996 | Abandoned |
Array
(
[id] => 3934241
[patent_doc_number] => 05952864
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Integratable circuit configuration for stabilizing the operating current of a transistor by negative feedback, being suitable in particular for battery-operated devices'
[patent_app_type] => 1
[patent_app_number] => 8/601329
[patent_app_country] => US
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[pdf_file] => patents/05/952/05952864.pdf
[firstpage_image] =>[orig_patent_app_number] => 601329
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/601329 | Integratable circuit configuration for stabilizing the operating current of a transistor by negative feedback, being suitable in particular for battery-operated devices | Feb 15, 1996 | Issued |