
Eunja Adolphe
Examiner (ID: 7947)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2504, 2816 |
| Total Applications | 291 |
| Issued Applications | 234 |
| Pending Applications | 14 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3837242
[patent_doc_number] => 05760630
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Input protection circuit having load resistor implemented by p-channel MIS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/599352
[patent_app_country] => US
[patent_app_date] => 1996-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3327
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760630.pdf
[firstpage_image] =>[orig_patent_app_number] => 599352
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/599352 | Input protection circuit having load resistor implemented by p-channel MIS transistor | Feb 8, 1996 | Issued |
| 08/595188 | A MASTER-SLAVE FLIP-FLOP CIRCUIT WITH BYPASS | Jan 31, 1996 | Abandoned |
| 08/595512 | DELAY CIRCUIT AND METHOD | Jan 31, 1996 | Abandoned |
Array
(
[id] => 3832426
[patent_doc_number] => 05783956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Semiconductor device realizing internal operation factor corresponding to an external operational factor stably regardless of fluctuation of the external operational factor'
[patent_app_type] => 1
[patent_app_number] => 8/594207
[patent_app_country] => US
[patent_app_date] => 1996-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 39
[patent_no_of_words] => 32793
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/783/05783956.pdf
[firstpage_image] =>[orig_patent_app_number] => 594207
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/594207 | Semiconductor device realizing internal operation factor corresponding to an external operational factor stably regardless of fluctuation of the external operational factor | Jan 30, 1996 | Issued |
Array
(
[id] => 3762071
[patent_doc_number] => 05721508
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => '5 Volt tolerant 3.3 volt output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/590588
[patent_app_country] => US
[patent_app_date] => 1996-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2031
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 348
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721508.pdf
[firstpage_image] =>[orig_patent_app_number] => 590588
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590588 | 5 Volt tolerant 3.3 volt output buffer | Jan 23, 1996 | Issued |
Array
(
[id] => 3894352
[patent_doc_number] => 05777493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Drive signal generating circuit for sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/581355
[patent_app_country] => US
[patent_app_date] => 1995-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3295
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 397
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/777/05777493.pdf
[firstpage_image] =>[orig_patent_app_number] => 581355
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/581355 | Drive signal generating circuit for sense amplifier | Dec 27, 1995 | Issued |
| 08/580173 | CHARACTERIZATION OF SELF TIMED CIRCUIT | Dec 27, 1995 | Abandoned |
| 08/575766 | DIGITAL PHASE SHIFTER | Dec 19, 1995 | Abandoned |
Array
(
[id] => 4033589
[patent_doc_number] => 05903174
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Method and apparatus for reducing skew among input signals within an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/575554
[patent_app_country] => US
[patent_app_date] => 1995-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 7092
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/903/05903174.pdf
[firstpage_image] =>[orig_patent_app_number] => 575554
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/575554 | Method and apparatus for reducing skew among input signals within an integrated circuit | Dec 19, 1995 | Issued |
Array
(
[id] => 3831787
[patent_doc_number] => 05731725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Precision delay circuit'
[patent_app_type] => 1
[patent_app_number] => 8/573304
[patent_app_country] => US
[patent_app_date] => 1995-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 8614
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731725.pdf
[firstpage_image] =>[orig_patent_app_number] => 573304
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573304 | Precision delay circuit | Dec 14, 1995 | Issued |
Array
(
[id] => 3801391
[patent_doc_number] => 05781039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Frequency controlled switch'
[patent_app_type] => 1
[patent_app_number] => 8/567804
[patent_app_country] => US
[patent_app_date] => 1995-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2346
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781039.pdf
[firstpage_image] =>[orig_patent_app_number] => 567804
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/567804 | Frequency controlled switch | Dec 5, 1995 | Issued |
Array
(
[id] => 3699990
[patent_doc_number] => 05680067
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Frequency dividing device'
[patent_app_type] => 1
[patent_app_number] => 8/559780
[patent_app_country] => US
[patent_app_date] => 1995-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 966
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/680/05680067.pdf
[firstpage_image] =>[orig_patent_app_number] => 559780
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/559780 | Frequency dividing device | Nov 14, 1995 | Issued |
Array
(
[id] => 3837821
[patent_doc_number] => 05712583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Clock phase alignment using frequency comparison'
[patent_app_type] => 1
[patent_app_number] => 8/556251
[patent_app_country] => US
[patent_app_date] => 1995-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2846
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/712/05712583.pdf
[firstpage_image] =>[orig_patent_app_number] => 556251
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/556251 | Clock phase alignment using frequency comparison | Nov 12, 1995 | Issued |
Array
(
[id] => 3625858
[patent_doc_number] => 05642071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Transit mixer with current mode input'
[patent_app_type] => 1
[patent_app_number] => 8/554448
[patent_app_country] => US
[patent_app_date] => 1995-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3261
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/642/05642071.pdf
[firstpage_image] =>[orig_patent_app_number] => 554448
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/554448 | Transit mixer with current mode input | Nov 6, 1995 | Issued |
Array
(
[id] => 3848589
[patent_doc_number] => 05708381
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Variable delay circuit'
[patent_app_type] => 1
[patent_app_number] => 8/551419
[patent_app_country] => US
[patent_app_date] => 1995-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 23
[patent_no_of_words] => 6804
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708381.pdf
[firstpage_image] =>[orig_patent_app_number] => 551419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/551419 | Variable delay circuit | Oct 31, 1995 | Issued |
Array
(
[id] => 3693320
[patent_doc_number] => 05696459
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'High voltage electronic amplifiers'
[patent_app_type] => 1
[patent_app_number] => 8/448554
[patent_app_country] => US
[patent_app_date] => 1995-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 12406
[patent_no_of_claims] => 19
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[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696459.pdf
[firstpage_image] =>[orig_patent_app_number] => 448554
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448554 | High voltage electronic amplifiers | Oct 22, 1995 | Issued |
Array
(
[id] => 3792833
[patent_doc_number] => 05736896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Signal processing circuit'
[patent_app_type] => 1
[patent_app_number] => 8/551913
[patent_app_country] => US
[patent_app_date] => 1995-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 9361
[patent_no_of_claims] => 39
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/736/05736896.pdf
[firstpage_image] =>[orig_patent_app_number] => 551913
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/551913 | Signal processing circuit | Oct 22, 1995 | Issued |
Array
(
[id] => 3728560
[patent_doc_number] => 05682114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-28
[patent_title] => 'Variable delay circuit, ring oscillator, and flip-flop circuit'
[patent_app_type] => 1
[patent_app_number] => 8/545320
[patent_app_country] => US
[patent_app_date] => 1995-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 32
[patent_no_of_words] => 13145
[patent_no_of_claims] => 16
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/682/05682114.pdf
[firstpage_image] =>[orig_patent_app_number] => 545320
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/545320 | Variable delay circuit, ring oscillator, and flip-flop circuit | Oct 18, 1995 | Issued |
Array
(
[id] => 3654296
[patent_doc_number] => 05684421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Compensated delay locked loop timing vernier'
[patent_app_type] => 1
[patent_app_number] => 8/542518
[patent_app_country] => US
[patent_app_date] => 1995-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4099
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684421.pdf
[firstpage_image] =>[orig_patent_app_number] => 542518
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542518 | Compensated delay locked loop timing vernier | Oct 12, 1995 | Issued |
| 08/539497 | CIRCUIT AND METHOD FOR GENERATING A DELAYED OUTPUT SIGNAL | Oct 5, 1995 | Abandoned |