| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3634774
[patent_doc_number] => 05686851
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Variable delay circuit'
[patent_app_type] => 1
[patent_app_number] => 8/539685
[patent_app_country] => US
[patent_app_date] => 1995-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 17
[patent_no_of_words] => 3975
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/686/05686851.pdf
[firstpage_image] =>[orig_patent_app_number] => 539685
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/539685 | Variable delay circuit | Oct 4, 1995 | Issued |
| 08/534650 | TIMING CONTROLLER AND CONTROLLED DELAY CIRCUIT FOR CONTROLLING TIMING OR DELAY TIME OF A SIGNAL BY CHANGING PHASE THEREOF | Sep 26, 1995 | Abandoned |
Array
(
[id] => 3752465
[patent_doc_number] => 05717353
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Clock signal generating circuit'
[patent_app_type] => 1
[patent_app_number] => 8/534388
[patent_app_country] => US
[patent_app_date] => 1995-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3743
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717353.pdf
[firstpage_image] =>[orig_patent_app_number] => 534388
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534388 | Clock signal generating circuit | Sep 26, 1995 | Issued |
Array
(
[id] => 3884991
[patent_doc_number] => 05748024
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Level convertor'
[patent_app_type] => 1
[patent_app_number] => 8/530483
[patent_app_country] => US
[patent_app_date] => 1995-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 3583
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748024.pdf
[firstpage_image] =>[orig_patent_app_number] => 530483
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/530483 | Level convertor | Sep 18, 1995 | Issued |
Array
(
[id] => 3831809
[patent_doc_number] => 05731727
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Voltage control type delay circuit and internal clock generation circuit using the same'
[patent_app_type] => 1
[patent_app_number] => 8/527968
[patent_app_country] => US
[patent_app_date] => 1995-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 7550
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731727.pdf
[firstpage_image] =>[orig_patent_app_number] => 527968
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/527968 | Voltage control type delay circuit and internal clock generation circuit using the same | Sep 13, 1995 | Issued |
| 08/525325 | PRECISION TIME INTERVAL DIVISION WITH DIGITAL PHASE DELAY LINES | Sep 7, 1995 | Abandoned |
Array
(
[id] => 3516664
[patent_doc_number] => 05563548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'Output voltage controlling circuit in a negative charge pump'
[patent_app_type] => 1
[patent_app_number] => 8/519137
[patent_app_country] => US
[patent_app_date] => 1995-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2374
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/563/05563548.pdf
[firstpage_image] =>[orig_patent_app_number] => 519137
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519137 | Output voltage controlling circuit in a negative charge pump | Aug 23, 1995 | Issued |
Array
(
[id] => 3626101
[patent_doc_number] => 05614855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Delay-locked loop'
[patent_app_type] => 1
[patent_app_number] => 8/512597
[patent_app_country] => US
[patent_app_date] => 1995-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 8456
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/614/05614855.pdf
[firstpage_image] =>[orig_patent_app_number] => 512597
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/512597 | Delay-locked loop | Aug 20, 1995 | Issued |
Array
(
[id] => 3730931
[patent_doc_number] => 05701097
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Statistically based current generator circuit'
[patent_app_type] => 1
[patent_app_number] => 8/515435
[patent_app_country] => US
[patent_app_date] => 1995-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4962
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/701/05701097.pdf
[firstpage_image] =>[orig_patent_app_number] => 515435
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/515435 | Statistically based current generator circuit | Aug 14, 1995 | Issued |
Array
(
[id] => 3666908
[patent_doc_number] => 05656967
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Two-stage fusible electrostatic discharge protection circuit'
[patent_app_type] => 1
[patent_app_number] => 8/511650
[patent_app_country] => US
[patent_app_date] => 1995-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2443
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656967.pdf
[firstpage_image] =>[orig_patent_app_number] => 511650
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/511650 | Two-stage fusible electrostatic discharge protection circuit | Aug 6, 1995 | Issued |
| 08/509238 | QUARTER-SQUARE MULTIPLIER BASED ON THE DYNAMIC BIAS CURRENT TECHNIQUE | Jul 30, 1995 | Abandoned |
Array
(
[id] => 3587537
[patent_doc_number] => 05581207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Synchronous delay line'
[patent_app_type] => 1
[patent_app_number] => 8/509116
[patent_app_country] => US
[patent_app_date] => 1995-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 10741
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581207.pdf
[firstpage_image] =>[orig_patent_app_number] => 509116
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/509116 | Synchronous delay line | Jul 27, 1995 | Issued |
Array
(
[id] => 3653417
[patent_doc_number] => 05629644
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Adjustable timer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/509035
[patent_app_country] => US
[patent_app_date] => 1995-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6365
[patent_no_of_claims] => 59
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/629/05629644.pdf
[firstpage_image] =>[orig_patent_app_number] => 509035
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/509035 | Adjustable timer circuit | Jul 27, 1995 | Issued |
| 08/507023 | VARIABLE IMPEDANCE DELAY ELEMENTS | Jul 24, 1995 | Abandoned |
Array
(
[id] => 3708717
[patent_doc_number] => 05675271
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Extended chip select reset apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 8/504502
[patent_app_country] => US
[patent_app_date] => 1995-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7280
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675271.pdf
[firstpage_image] =>[orig_patent_app_number] => 504502
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/504502 | Extended chip select reset apparatus and method | Jul 19, 1995 | Issued |
Array
(
[id] => 3663517
[patent_doc_number] => 05627488
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-06
[patent_title] => 'Delay circuit, oscillation circuit and semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/494010
[patent_app_country] => US
[patent_app_date] => 1995-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
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[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/627/05627488.pdf
[firstpage_image] =>[orig_patent_app_number] => 494010
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/494010 | Delay circuit, oscillation circuit and semiconductor memory device | Jun 22, 1995 | Issued |
Array
(
[id] => 3593620
[patent_doc_number] => 05550500
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Timing delay modulation scheme for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/493901
[patent_app_country] => US
[patent_app_date] => 1995-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3706
[patent_no_of_claims] => 23
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[patent_words_short_claim] => 153
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550500.pdf
[firstpage_image] =>[orig_patent_app_number] => 493901
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/493901 | Timing delay modulation scheme for integrated circuits | Jun 22, 1995 | Issued |
| 08/490331 | PARALLEL VOLTAGE CONTROLLED RESISTANCE ELEMENTS | Jun 12, 1995 | Abandoned |
| 08/478534 | CLOCK GENERATOR WITH PROGRAMMABLE NON-OVERLAPPING-CLOCK-EDGE-CAPABILITY | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3525936
[patent_doc_number] => 05530401
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Single source differential circuit'
[patent_app_type] => 1
[patent_app_number] => 8/483906
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2999
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/530/05530401.pdf
[firstpage_image] =>[orig_patent_app_number] => 483906
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/483906 | Single source differential circuit | Jun 6, 1995 | Issued |