Search

Eva Y. Montalvo

Supervisory Patent Examiner (ID: 9223, Phone: (571)270-3829 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2800, 4158, 2814, 2817, 2818, 2899
Total Applications
376
Issued Applications
278
Pending Applications
18
Abandoned Applications
83

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8323995 [patent_doc_number] => 20120196406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'Semiconductor Package with Embedded Die' [patent_app_type] => utility [patent_app_number] => 13/441691 [patent_app_country] => US [patent_app_date] => 2012-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5437 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441691 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/441691
Semiconductor device and method of forming stud bumps over embedded die Apr 5, 2012 Issued
Array ( [id] => 9469654 [patent_doc_number] => 08723289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Interconnection wiring structure of a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/423463 [patent_app_country] => US [patent_app_date] => 2012-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8122 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13423463 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/423463
Interconnection wiring structure of a semiconductor memory device Mar 18, 2012 Issued
Array ( [id] => 8249150 [patent_doc_number] => 20120153472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core' [patent_app_type] => utility [patent_app_number] => 13/405094 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12883 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153472.pdf [firstpage_image] =>[orig_patent_app_number] => 13405094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405094
Semiconductor device and method of providing Z-interconnect conductive pillars with inner polymer core Feb 23, 2012 Issued
Array ( [id] => 9286795 [patent_doc_number] => 08643126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Self aligned silicided contacts' [patent_app_type] => utility [patent_app_number] => 13/365418 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 44 [patent_no_of_words] => 7913 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/365418
Self aligned silicided contacts Feb 2, 2012 Issued
Array ( [id] => 9299742 [patent_doc_number] => 08647969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-11 [patent_title] => 'Method for forming a semiconductor layer with improved gap filling properties' [patent_app_type] => utility [patent_app_number] => 13/362899 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362899
Method for forming a semiconductor layer with improved gap filling properties Jan 30, 2012 Issued
Array ( [id] => 8725430 [patent_doc_number] => 08404545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Tunnel field-effect transistor with gated tunnel barrier' [patent_app_type] => utility [patent_app_number] => 13/353607 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 14279 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13353607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/353607
Tunnel field-effect transistor with gated tunnel barrier Jan 18, 2012 Issued
Array ( [id] => 8037129 [patent_doc_number] => 20120068298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/307878 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12772 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20120068298.pdf [firstpage_image] =>[orig_patent_app_number] => 13307878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307878
Semiconductor device having super junction structure and method for manufacturing the same Nov 29, 2011 Issued
Array ( [id] => 8237466 [patent_doc_number] => 20120146204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'SEMICONDUCTOR DEVICES AND ELECTRICAL PARTS MANUFACTURING USING METAL COATED WIRES' [patent_app_type] => utility [patent_app_number] => 13/295516 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2716 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13295516 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/295516
SEMICONDUCTOR DEVICES AND ELECTRICAL PARTS MANUFACTURING USING METAL COATED WIRES Nov 13, 2011 Abandoned
Array ( [id] => 8664292 [patent_doc_number] => 08377753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of fabricating a semiconductor device having a resin with warpage compensated structures' [patent_app_type] => utility [patent_app_number] => 13/293844 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 2428 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/293844
Method of fabricating a semiconductor device having a resin with warpage compensated structures Nov 9, 2011 Issued
Array ( [id] => 7783196 [patent_doc_number] => 20120044752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'HIGH DENSITY INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/285182 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10395 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20120044752.pdf [firstpage_image] =>[orig_patent_app_number] => 13285182 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285182
High density integrated circuitry for semiconductor memory having memory cells with a minimum capable photolithographic feature dimension Oct 30, 2011 Issued
Array ( [id] => 9009262 [patent_doc_number] => 08524558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET' [patent_app_type] => utility [patent_app_number] => 13/200882 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2539 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13200882 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/200882
Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET Oct 3, 2011 Issued
Array ( [id] => 8154531 [patent_doc_number] => 20120097933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'ORGANIC EL DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/248437 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 21898 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20120097933.pdf [firstpage_image] =>[orig_patent_app_number] => 13248437 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248437
Organic EL display device and manufacturing method of the same Sep 28, 2011 Issued
Array ( [id] => 7669643 [patent_doc_number] => 20110318912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Methods for preparing a semiconductor wafer with high thermal conductivity' [patent_app_type] => utility [patent_app_number] => 13/199587 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6888 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13199587 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/199587
Methods for preparing a semiconductor wafer with high thermal conductivity Sep 1, 2011 Issued
Array ( [id] => 7651402 [patent_doc_number] => 20110300671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'LEADFRAME-BASED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/214076 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4195 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20110300671.pdf [firstpage_image] =>[orig_patent_app_number] => 13214076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214076
Fabrication method of leadframe-based semiconductor package Aug 18, 2011 Issued
Array ( [id] => 8846757 [patent_doc_number] => 08455944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Semiconductor device having a trench-gate transistor' [patent_app_type] => utility [patent_app_number] => 13/185912 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 66 [patent_no_of_words] => 5772 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185912
Semiconductor device having a trench-gate transistor Jul 18, 2011 Issued
Array ( [id] => 7570996 [patent_doc_number] => 20110266652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/181838 [patent_app_country] => US [patent_app_date] => 2011-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3758 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266652.pdf [firstpage_image] =>[orig_patent_app_number] => 13181838 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/181838
Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof Jul 12, 2011 Issued
Array ( [id] => 8519859 [patent_doc_number] => 20120319267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/163611 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163611
Integrated circuit packaging system with thermal dispersal structures and method of manufacture thereof Jun 16, 2011 Issued
Array ( [id] => 8519799 [patent_doc_number] => 20120319207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'SEMICONDUCTOR DEVICE WITH THRESHOLD VOLTAGE CONTROL AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/162825 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162825
SEMICONDUCTOR DEVICE WITH THRESHOLD VOLTAGE CONTROL AND METHOD OF FABRICATING THE SAME Jun 16, 2011 Abandoned
Array ( [id] => 9582934 [patent_doc_number] => 08772937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Semiconductor device including inner interconnection structure able to conduct signals or voltages in the semiconductor chip with vertical connection vias and horizontal buried conductive lines' [patent_app_type] => utility [patent_app_number] => 13/162775 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162775
Semiconductor device including inner interconnection structure able to conduct signals or voltages in the semiconductor chip with vertical connection vias and horizontal buried conductive lines Jun 16, 2011 Issued
Array ( [id] => 8519737 [patent_doc_number] => 20120319145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'Non-Common Capping Layer on an Organic Device' [patent_app_type] => utility [patent_app_number] => 13/163132 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 18535 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163132
Non-common capping layer on an organic device Jun 16, 2011 Issued
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