
Evan Garrett Clinton
Examiner (ID: 713, Phone: (571)270-0525 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2816 |
| Total Applications | 663 |
| Issued Applications | 542 |
| Pending Applications | 74 |
| Abandoned Applications | 65 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15250097
[patent_doc_number] => 10510577
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-17
[patent_title] => Lift off process for chip scale package solid state devices on engineered substrate
[patent_app_type] => utility
[patent_app_number] => 15/974606
[patent_app_country] => US
[patent_app_date] => 2018-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4323
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974606
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/974606 | Lift off process for chip scale package solid state devices on engineered substrate | May 7, 2018 | Issued |
Array
(
[id] => 16601610
[patent_doc_number] => 20210028141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-28
[patent_title] => Electrical Interconnection Of Circuit Elements On A Substrate Without Prior Patterning
[patent_app_type] => utility
[patent_app_number] => 16/495112
[patent_app_country] => US
[patent_app_date] => 2018-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4428
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16495112
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/495112 | Electrical interconnection of circuit elements on a substrate without prior patterning | Apr 25, 2018 | Issued |
Array
(
[id] => 15823089
[patent_doc_number] => 10636740
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Semiconductor device, method for manufacturing semiconductor device, and interface unit
[patent_app_type] => utility
[patent_app_number] => 15/934256
[patent_app_country] => US
[patent_app_date] => 2018-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 13705
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934256
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/934256 | Semiconductor device, method for manufacturing semiconductor device, and interface unit | Mar 22, 2018 | Issued |
Array
(
[id] => 14738249
[patent_doc_number] => 10388534
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-20
[patent_title] => Method of processing workpiece
[patent_app_type] => utility
[patent_app_number] => 15/934443
[patent_app_country] => US
[patent_app_date] => 2018-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 6114
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934443
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/934443 | Method of processing workpiece | Mar 22, 2018 | Issued |
Array
(
[id] => 17078183
[patent_doc_number] => 11114599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Electronic devices including solid semiconductor dies
[patent_app_type] => utility
[patent_app_number] => 16/498478
[patent_app_country] => US
[patent_app_date] => 2018-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 27
[patent_no_of_words] => 6823
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16498478
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/498478 | Electronic devices including solid semiconductor dies | Mar 21, 2018 | Issued |
Array
(
[id] => 14843385
[patent_doc_number] => 20190280093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => High Electron Mobility Transistor with Deep Charge Carrier Gas Contact Structure
[patent_app_type] => utility
[patent_app_number] => 15/913284
[patent_app_country] => US
[patent_app_date] => 2018-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7111
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913284
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/913284 | High electron mobility transistor with deep charge carrier gas contact structure | Mar 5, 2018 | Issued |
Array
(
[id] => 13420135
[patent_doc_number] => 20180261610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-13
[patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/913297
[patent_app_country] => US
[patent_app_date] => 2018-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7021
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913297
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/913297 | Semiconductor structure and fabrication method thereof | Mar 5, 2018 | Issued |
Array
(
[id] => 14079945
[patent_doc_number] => 20190088860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-21
[patent_title] => MAGNETIC MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/913377
[patent_app_country] => US
[patent_app_date] => 2018-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10812
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913377
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/913377 | Magnetic memory | Mar 5, 2018 | Issued |
Array
(
[id] => 15352059
[patent_doc_number] => 20200013921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => METHOD FOR MANUFACTURING A DONOR SUBSTRATE FOR MAKING OPTOELECTRONIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/487037
[patent_app_country] => US
[patent_app_date] => 2018-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4507
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487037
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/487037 | Method for manufacturing a donor substrate for making optoelectronic devices | Feb 25, 2018 | Issued |
Array
(
[id] => 15611271
[patent_doc_number] => 10586705
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Fluorine doped non-volatile memory cells and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 15/904041
[patent_app_country] => US
[patent_app_date] => 2018-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4954
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904041
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/904041 | Fluorine doped non-volatile memory cells and methods for forming the same | Feb 22, 2018 | Issued |
Array
(
[id] => 13832769
[patent_doc_number] => 20190019869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-17
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/888074
[patent_app_country] => US
[patent_app_date] => 2018-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3703
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888074
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/888074 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Feb 3, 2018 | Abandoned |
Array
(
[id] => 14491981
[patent_doc_number] => 10332789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-25
[patent_title] => Semiconductor device with TiN adhesion layer for forming a contact plug
[patent_app_type] => utility
[patent_app_number] => 15/887819
[patent_app_country] => US
[patent_app_date] => 2018-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 42
[patent_no_of_words] => 8591
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887819
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/887819 | Semiconductor device with TiN adhesion layer for forming a contact plug | Feb 1, 2018 | Issued |
Array
(
[id] => 14691569
[patent_doc_number] => 20190244900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => Power Distribution Circuitry
[patent_app_type] => utility
[patent_app_number] => 15/887972
[patent_app_country] => US
[patent_app_date] => 2018-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4548
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887972
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/887972 | Power distribution circuitry | Feb 1, 2018 | Issued |
Array
(
[id] => 14691679
[patent_doc_number] => 20190244955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => HIGH SWITCHING FREQUENCY, LOW LOSS AND SMALL FORM FACTOR FULLY INTEGRATED POWER STAGE
[patent_app_type] => utility
[patent_app_number] => 15/887589
[patent_app_country] => US
[patent_app_date] => 2018-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6391
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887589
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/887589 | High switching frequency, low loss and small form factor fully integrated power stage | Feb 1, 2018 | Issued |
Array
(
[id] => 14573383
[patent_doc_number] => 20190214299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => Separation of workpiece with three material removal stages
[patent_app_type] => utility
[patent_app_number] => 15/863954
[patent_app_country] => US
[patent_app_date] => 2018-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9886
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863954
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863954 | Separation of workpiece with three material removal stages | Jan 6, 2018 | Issued |
Array
(
[id] => 12918124
[patent_doc_number] => 20180197884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/863009
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29831
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863009
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863009 | Semiconductor device | Jan 4, 2018 | Issued |
Array
(
[id] => 12917956
[patent_doc_number] => 20180197828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => VANISHING VIA FOR HARDWARE IP PROTECTION FROM REVERSE ENGINEERING
[patent_app_type] => utility
[patent_app_number] => 15/863133
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5012
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863133
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863133 | Vanishing via for hardware IP protection from reverse engineering | Jan 4, 2018 | Issued |
Array
(
[id] => 14573471
[patent_doc_number] => 20190214343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => REPLACEMENT METAL GATE PROCESSES FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 15/862930
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11474
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862930
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/862930 | Replacement metal gate processes for vertical transport field-effect transistor | Jan 4, 2018 | Issued |
Array
(
[id] => 14573395
[patent_doc_number] => 20190214305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => Techniques for Forming Different Gate Length Vertical Transistors with Dual Gate Oxide
[patent_app_type] => utility
[patent_app_number] => 15/863000
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863000
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863000 | Techniques for forming different gate length vertical transistors with dual gate oxide | Jan 4, 2018 | Issued |
Array
(
[id] => 12909985
[patent_doc_number] => 20180195171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => DEPOSITION METHOD
[patent_app_type] => utility
[patent_app_number] => 15/863700
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4509
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863700
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863700 | Deposition method | Jan 4, 2018 | Issued |