Search

Evan Garrett Clinton

Examiner (ID: 713, Phone: (571)270-0525 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2816
Total Applications
663
Issued Applications
542
Pending Applications
74
Abandoned Applications
65

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18586023 [patent_doc_number] => 20230268288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/111302 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/111302
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Feb 16, 2023 Pending
Array ( [id] => 20705936 [patent_doc_number] => 12628668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/109392 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109392
Semiconductor package Feb 13, 2023 Issued
Array ( [id] => 19414820 [patent_doc_number] => 12080657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Die embedded in substrate with stress buffer [patent_app_type] => utility [patent_app_number] => 18/168319 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168319
Die embedded in substrate with stress buffer Feb 12, 2023 Issued
Array ( [id] => 19206221 [patent_doc_number] => 20240178120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/166450 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166450 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166450
Integrated fan-out package and manufacturing method thereof Feb 7, 2023 Issued
Array ( [id] => 19654499 [patent_doc_number] => 12176299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/164554 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 33 [patent_no_of_words] => 10928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164554
Semiconductor device and manufacturing method thereof Feb 2, 2023 Issued
Array ( [id] => 19906530 [patent_doc_number] => 12283549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => High density interconnection using fanout interposer chiplet [patent_app_type] => utility [patent_app_number] => 18/163033 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 1076 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163033 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163033
High density interconnection using fanout interposer chiplet Jan 31, 2023 Issued
Array ( [id] => 18379792 [patent_doc_number] => 20230154881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => PACKAGE STRUCTURE INCLUDING IPD AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/155705 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155705
Package structure including IPD and method of forming the same Jan 16, 2023 Issued
Array ( [id] => 19285824 [patent_doc_number] => 20240222301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHODS AND APPARATUS FOR OPTICAL THERMAL TREATMENT IN SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 18/147497 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18147497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/147497
METHODS AND APPARATUS FOR OPTICAL THERMAL TREATMENT IN SEMICONDUCTOR PACKAGES Dec 27, 2022 Pending
Array ( [id] => 19670941 [patent_doc_number] => 12183712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Method and system for manufacturing a semiconductor package structure [patent_app_type] => utility [patent_app_number] => 18/089458 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5942 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089458
Method and system for manufacturing a semiconductor package structure Dec 26, 2022 Issued
Array ( [id] => 20312027 [patent_doc_number] => 20250329656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => APPARATUS, SYSTEM, AND METHOD FOR INTEGRATING PASSIVE ELEMENTS INTO ELECTRONIC BRIDGE COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/088908 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088908
APPARATUS, SYSTEM, AND METHOD FOR INTEGRATING PASSIVE ELEMENTS INTO ELECTRONIC BRIDGE COMPONENTS Dec 26, 2022 Pending
Array ( [id] => 18323493 [patent_doc_number] => 20230121621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/086185 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086185
Semiconductor devices and methods of manufacturing semiconductor devices Dec 20, 2022 Issued
Array ( [id] => 20598225 [patent_doc_number] => 12581965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Packaging structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/077149 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 3124 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077149
Packaging structure and manufacturing method thereof Dec 6, 2022 Issued
Array ( [id] => 19221597 [patent_doc_number] => 20240186301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DOUBLE-SIDED MULTICHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 18/062445 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062445
Double-sided multichip packages Dec 5, 2022 Issued
Array ( [id] => 19221599 [patent_doc_number] => 20240186303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => MULTICHIP PACKAGES WITH 3D INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/062166 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062166 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062166
Multichip packages with 3D integration Dec 5, 2022 Issued
Array ( [id] => 19221566 [patent_doc_number] => 20240186270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => MICROELECTRONIC ASSEMBLY HAVING ANTIFERROMAGNETIC FILM STRUCTURE THEREIN [patent_app_type] => utility [patent_app_number] => 18/074253 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18074253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/074253
MICROELECTRONIC ASSEMBLY HAVING ANTIFERROMAGNETIC FILM STRUCTURE THEREIN Dec 1, 2022 Pending
Array ( [id] => 20416858 [patent_doc_number] => 12500152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Power semiconductor module, method for assembling a power semiconductor module and housing for a power semiconductor module [patent_app_type] => utility [patent_app_number] => 18/070552 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2346 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070552
Power semiconductor module, method for assembling a power semiconductor module and housing for a power semiconductor module Nov 28, 2022 Issued
Array ( [id] => 20705979 [patent_doc_number] => 12628711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Integrated circuit package, electronic device including the same, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/070825 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3251 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070825 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070825
Integrated circuit package, electronic device including the same, and manufacturing method thereof Nov 28, 2022 Issued
Array ( [id] => 20318137 [patent_doc_number] => 12456692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Microelectronic package RDL patterns to reduce stress in RDLs across components [patent_app_type] => utility [patent_app_number] => 18/058991 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058991
Microelectronic package RDL patterns to reduce stress in RDLs across components Nov 27, 2022 Issued
Array ( [id] => 20375357 [patent_doc_number] => 12482801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/994880 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 7622 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994880
Semiconductor package Nov 27, 2022 Issued
Array ( [id] => 18857447 [patent_doc_number] => 11855043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-26 [patent_title] => Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates [patent_app_type] => utility [patent_app_number] => 17/994205 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7894 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994205
Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates Nov 24, 2022 Issued
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