Search

Evan H. Macfarlane

Examiner (ID: 10956, Phone: (303)297-4242 , Office: P/3724 )

Most Active Art Unit
3724
Art Unit(s)
3724
Total Applications
573
Issued Applications
247
Pending Applications
83
Abandoned Applications
259

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4365114 [patent_doc_number] => 06191495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Micromagnetic device having an anisotropic ferromagnetic core and method of manufacture therefor' [patent_app_type] => 1 [patent_app_number] => 9/292860 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5301 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191495.pdf [firstpage_image] =>[orig_patent_app_number] => 292860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292860
Micromagnetic device having an anisotropic ferromagnetic core and method of manufacture therefor Apr 15, 1999 Issued
09/288884 HETEROSTRUCTURE SPHERICAL SHAPED SEMICONDUCTOR DEVICE Apr 8, 1999 Abandoned
Array ( [id] => 1602606 [patent_doc_number] => 06432785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide' [patent_app_type] => B1 [patent_app_number] => 09/275136 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432785.pdf [firstpage_image] =>[orig_patent_app_number] => 09275136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275136
Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide Mar 22, 1999 Issued
Array ( [id] => 1553538 [patent_doc_number] => 06348390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method for fabricating MOSFETS with a recessed self-aligned silicide contact and extended source/drain junctions' [patent_app_type] => B1 [patent_app_number] => 09/275135 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348390.pdf [firstpage_image] =>[orig_patent_app_number] => 09275135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275135
Method for fabricating MOSFETS with a recessed self-aligned silicide contact and extended source/drain junctions Mar 22, 1999 Issued
Array ( [id] => 1378993 [patent_doc_number] => 06555438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions' [patent_app_type] => B1 [patent_app_number] => 09/275134 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555438.pdf [firstpage_image] =>[orig_patent_app_number] => 09275134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275134
Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions Mar 22, 1999 Issued
Array ( [id] => 1188862 [patent_doc_number] => 06734093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method for placing active circuits beneath active bonding pads' [patent_app_type] => B1 [patent_app_number] => 09/271615 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1906 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734093.pdf [firstpage_image] =>[orig_patent_app_number] => 09271615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271615
Method for placing active circuits beneath active bonding pads Mar 16, 1999 Issued
Array ( [id] => 4368616 [patent_doc_number] => 06287911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device with silicide layers and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/260349 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 9011 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287911.pdf [firstpage_image] =>[orig_patent_app_number] => 260349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260349
Semiconductor device with silicide layers and fabrication method thereof Mar 1, 1999 Issued
Array ( [id] => 4302953 [patent_doc_number] => 06187663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials' [patent_app_type] => 1 [patent_app_number] => 9/234059 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2391 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187663.pdf [firstpage_image] =>[orig_patent_app_number] => 234059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234059
Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials Jan 18, 1999 Issued
Array ( [id] => 4350591 [patent_doc_number] => 06291316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for fabricating passivated semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/233706 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1928 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291316.pdf [firstpage_image] =>[orig_patent_app_number] => 233706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233706
Method for fabricating passivated semiconductor devices Jan 18, 1999 Issued
Array ( [id] => 4327557 [patent_doc_number] => 06319833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Chemically preventing copper dendrite formation and growth by spraying' [patent_app_type] => 1 [patent_app_number] => 9/207318 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4589 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319833.pdf [firstpage_image] =>[orig_patent_app_number] => 207318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207318
Chemically preventing copper dendrite formation and growth by spraying Dec 6, 1998 Issued
Array ( [id] => 4405280 [patent_doc_number] => 06271130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Semiconductor assisted metal deposition for nanolithography applications' [patent_app_type] => 1 [patent_app_number] => 9/200159 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5014 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271130.pdf [firstpage_image] =>[orig_patent_app_number] => 200159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200159
Semiconductor assisted metal deposition for nanolithography applications Nov 24, 1998 Issued
09/199689 SEMICONDUCTOR DEVICE HAVING DUMMY INTERCONNECTION AND METHOD FOR MANUFACTURING THE SAME Nov 24, 1998 Abandoned
09/178199 OPTOELECTRONIC COMPONENT AND METHOD FOR ITS PRODUCTION Oct 22, 1998 Abandoned
Array ( [id] => 4277758 [patent_doc_number] => 06323519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process' [patent_app_type] => 1 [patent_app_number] => 9/177871 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6490 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323519.pdf [firstpage_image] =>[orig_patent_app_number] => 177871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177871
Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process Oct 22, 1998 Issued
Array ( [id] => 4412938 [patent_doc_number] => 06239476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Integrated circuit isolation structure employing a protective layer and method for making same' [patent_app_type] => 1 [patent_app_number] => 9/176132 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6212 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239476.pdf [firstpage_image] =>[orig_patent_app_number] => 176132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176132
Integrated circuit isolation structure employing a protective layer and method for making same Oct 20, 1998 Issued
Array ( [id] => 4117182 [patent_doc_number] => 06071812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes' [patent_app_type] => 1 [patent_app_number] => 9/174622 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2875 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071812.pdf [firstpage_image] =>[orig_patent_app_number] => 174622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174622
Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes Oct 18, 1998 Issued
Array ( [id] => 4086563 [patent_doc_number] => 06133071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package' [patent_app_type] => 1 [patent_app_number] => 9/172862 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2159 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133071.pdf [firstpage_image] =>[orig_patent_app_number] => 172862 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172862
Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package Oct 14, 1998 Issued
Array ( [id] => 4359387 [patent_doc_number] => 06169035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method of local oxidation using etchant and oxidizer' [patent_app_type] => 1 [patent_app_number] => 9/173153 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169035.pdf [firstpage_image] =>[orig_patent_app_number] => 173153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173153
Method of local oxidation using etchant and oxidizer Oct 13, 1998 Issued
Array ( [id] => 4083546 [patent_doc_number] => 06162664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method for fabricating a surface mounting type semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 9/168886 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3490 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162664.pdf [firstpage_image] =>[orig_patent_app_number] => 168886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/168886
Method for fabricating a surface mounting type semiconductor chip package Oct 8, 1998 Issued
Array ( [id] => 4185948 [patent_doc_number] => 06093628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application' [patent_app_type] => 1 [patent_app_number] => 9/165003 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2711 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093628.pdf [firstpage_image] =>[orig_patent_app_number] => 165003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165003
Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application Sep 30, 1998 Issued
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