
Evan H. Macfarlane
Examiner (ID: 10956, Phone: (303)297-4242 , Office: P/3724 )
| Most Active Art Unit | 3724 |
| Art Unit(s) | 3724 |
| Total Applications | 573 |
| Issued Applications | 247 |
| Pending Applications | 83 |
| Abandoned Applications | 259 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3910591
[patent_doc_number] => 06001682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method of fabricating cylinder capacitors'
[patent_app_type] => 1
[patent_app_number] => 9/059319
[patent_app_country] => US
[patent_app_date] => 1998-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 2175
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001682.pdf
[firstpage_image] =>[orig_patent_app_number] => 059319
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/059319 | Method of fabricating cylinder capacitors | Apr 12, 1998 | Issued |
Array
(
[id] => 4129990
[patent_doc_number] => 06033950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Dual layer poly deposition to prevent auto-doping in mixed-mode product fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/058127
[patent_app_country] => US
[patent_app_date] => 1998-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2797
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/033/06033950.pdf
[firstpage_image] =>[orig_patent_app_number] => 058127
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/058127 | Dual layer poly deposition to prevent auto-doping in mixed-mode product fabrication | Apr 9, 1998 | Issued |
Array
(
[id] => 4265955
[patent_doc_number] => 06259142
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Multiple split gate semiconductor device and fabrication method'
[patent_app_type] => 1
[patent_app_number] => 9/056837
[patent_app_country] => US
[patent_app_date] => 1998-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 5805
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/259/06259142.pdf
[firstpage_image] =>[orig_patent_app_number] => 056837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/056837 | Multiple split gate semiconductor device and fabrication method | Apr 6, 1998 | Issued |
Array
(
[id] => 4080754
[patent_doc_number] => 06054350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'EPROM cell having a gate structure with sidewall spacers of differential composition'
[patent_app_type] => 1
[patent_app_number] => 9/054358
[patent_app_country] => US
[patent_app_date] => 1998-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 6282
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/054/06054350.pdf
[firstpage_image] =>[orig_patent_app_number] => 054358
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/054358 | EPROM cell having a gate structure with sidewall spacers of differential composition | Apr 1, 1998 | Issued |
Array
(
[id] => 4098162
[patent_doc_number] => 06048791
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Semiconductor device with electrode formed of conductive layer consisting of polysilicon layer and metal-silicide layer and its manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/050357
[patent_app_country] => US
[patent_app_date] => 1998-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 3118
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/048/06048791.pdf
[firstpage_image] =>[orig_patent_app_number] => 050357
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050357 | Semiconductor device with electrode formed of conductive layer consisting of polysilicon layer and metal-silicide layer and its manufacturing method | Mar 30, 1998 | Issued |
Array
(
[id] => 4116603
[patent_doc_number] => 06071772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Method of fabricating a semiconductor memory device having a tree-type capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/050899
[patent_app_country] => US
[patent_app_date] => 1998-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 36
[patent_no_of_words] => 7282
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/071/06071772.pdf
[firstpage_image] =>[orig_patent_app_number] => 050899
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050899 | Method of fabricating a semiconductor memory device having a tree-type capacitor | Mar 30, 1998 | Issued |
Array
(
[id] => 4084424
[patent_doc_number] => 06025219
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Method of manufacturing a semiconductor device having MOS transistor and bipolar transistor in mixture on the same substrate'
[patent_app_type] => 1
[patent_app_number] => 9/049929
[patent_app_country] => US
[patent_app_date] => 1998-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 25
[patent_no_of_words] => 7684
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025219.pdf
[firstpage_image] =>[orig_patent_app_number] => 049929
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/049929 | Method of manufacturing a semiconductor device having MOS transistor and bipolar transistor in mixture on the same substrate | Mar 29, 1998 | Issued |
Array
(
[id] => 4064027
[patent_doc_number] => 06008099
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion'
[patent_app_type] => 1
[patent_app_number] => 9/050689
[patent_app_country] => US
[patent_app_date] => 1998-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 12
[patent_no_of_words] => 5212
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/008/06008099.pdf
[firstpage_image] =>[orig_patent_app_number] => 050689
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050689 | Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion | Mar 29, 1998 | Issued |
Array
(
[id] => 3911014
[patent_doc_number] => 06001710
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'MOSFET device having recessed gate-drain shield and method'
[patent_app_type] => 1
[patent_app_number] => 9/050859
[patent_app_country] => US
[patent_app_date] => 1998-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 1722
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001710.pdf
[firstpage_image] =>[orig_patent_app_number] => 050859
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050859 | MOSFET device having recessed gate-drain shield and method | Mar 29, 1998 | Issued |
Array
(
[id] => 3993368
[patent_doc_number] => 05985696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method for producing an optoelectronic semiconductor component'
[patent_app_type] => 1
[patent_app_number] => 9/048561
[patent_app_country] => US
[patent_app_date] => 1998-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3721
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/985/05985696.pdf
[firstpage_image] =>[orig_patent_app_number] => 048561
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/048561 | Method for producing an optoelectronic semiconductor component | Mar 25, 1998 | Issued |
Array
(
[id] => 4215018
[patent_doc_number] => 06110822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Method for forming a polysilicon-interconnect contact in a TFT-SRAM'
[patent_app_type] => 1
[patent_app_number] => 9/047539
[patent_app_country] => US
[patent_app_date] => 1998-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 4655
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/110/06110822.pdf
[firstpage_image] =>[orig_patent_app_number] => 047539
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/047539 | Method for forming a polysilicon-interconnect contact in a TFT-SRAM | Mar 24, 1998 | Issued |
Array
(
[id] => 4417315
[patent_doc_number] => 06194290
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Methods for making semiconductor devices by low temperature direct bonding'
[patent_app_type] => 1
[patent_app_number] => 9/037723
[patent_app_country] => US
[patent_app_date] => 1998-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 29
[patent_no_of_words] => 12039
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194290.pdf
[firstpage_image] =>[orig_patent_app_number] => 037723
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/037723 | Methods for making semiconductor devices by low temperature direct bonding | Mar 8, 1998 | Issued |
Array
(
[id] => 7643513
[patent_doc_number] => 06429528
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Multichip semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/032191
[patent_app_country] => US
[patent_app_date] => 1998-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4189
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429528.pdf
[firstpage_image] =>[orig_patent_app_number] => 09032191
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/032191 | Multichip semiconductor package | Feb 26, 1998 | Issued |
Array
(
[id] => 6959548
[patent_doc_number] => 20010011740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-09
[patent_title] => 'CAPACITOR HAVING TANTALUM OXYNITRIDE FILM AND METHOD FOR MAKING SAME'
[patent_app_type] => new
[patent_app_number] => 09/031526
[patent_app_country] => US
[patent_app_date] => 1998-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4075
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20010011740.pdf
[firstpage_image] =>[orig_patent_app_number] => 09031526
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/031526 | Capacitor having tantalum oxynitride film and method for making same | Feb 25, 1998 | Issued |
Array
(
[id] => 4420911
[patent_doc_number] => 06225241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'Catalytic deposition method for a semiconductor surface passivation film'
[patent_app_type] => 1
[patent_app_number] => 9/007543
[patent_app_country] => US
[patent_app_date] => 1998-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 3432
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/225/06225241.pdf
[firstpage_image] =>[orig_patent_app_number] => 007543
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/007543 | Catalytic deposition method for a semiconductor surface passivation film | Jan 14, 1998 | Issued |
Array
(
[id] => 4394389
[patent_doc_number] => 06297078
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Integrated circuit package with bond wires at the corners of an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/001636
[patent_app_country] => US
[patent_app_date] => 1997-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1304
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/297/06297078.pdf
[firstpage_image] =>[orig_patent_app_number] => 001636
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/001636 | Integrated circuit package with bond wires at the corners of an integrated circuit | Dec 30, 1997 | Issued |
Array
(
[id] => 4405773
[patent_doc_number] => 06171907
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Method for fabricating tunnel window in EEPROM cell with reduced cell pitch'
[patent_app_type] => 1
[patent_app_number] => 8/994101
[patent_app_country] => US
[patent_app_date] => 1997-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4083
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/171/06171907.pdf
[firstpage_image] =>[orig_patent_app_number] => 994101
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994101 | Method for fabricating tunnel window in EEPROM cell with reduced cell pitch | Dec 18, 1997 | Issued |
Array
(
[id] => 4004225
[patent_doc_number] => 05960285
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Flash EEPROM device'
[patent_app_type] => 1
[patent_app_number] => 8/975490
[patent_app_country] => US
[patent_app_date] => 1997-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4430
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/960/05960285.pdf
[firstpage_image] =>[orig_patent_app_number] => 975490
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/975490 | Flash EEPROM device | Nov 20, 1997 | Issued |
Array
(
[id] => 3943580
[patent_doc_number] => 05976934
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Method of manufacturing a nonvolatile semiconductor memory device with select gate bird\'s beaks'
[patent_app_type] => 1
[patent_app_number] => 8/971125
[patent_app_country] => US
[patent_app_date] => 1997-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 32
[patent_no_of_words] => 8181
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/976/05976934.pdf
[firstpage_image] =>[orig_patent_app_number] => 971125
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971125 | Method of manufacturing a nonvolatile semiconductor memory device with select gate bird's beaks | Nov 19, 1997 | Issued |
Array
(
[id] => 4137173
[patent_doc_number] => 06034414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Variable capacitor using resistor generated heat to control dielectric thickness'
[patent_app_type] => 1
[patent_app_number] => 8/972810
[patent_app_country] => US
[patent_app_date] => 1997-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 24
[patent_no_of_words] => 3909
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/034/06034414.pdf
[firstpage_image] =>[orig_patent_app_number] => 972810
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/972810 | Variable capacitor using resistor generated heat to control dielectric thickness | Nov 17, 1997 | Issued |