Search

Evelyn Y. Pyla

Examiner (ID: 18932, Phone: (571)270-7366 , Office: P/1651 )

Most Active Art Unit
1633
Art Unit(s)
1651, 1633, 4141
Total Applications
656
Issued Applications
307
Pending Applications
85
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9834458 [patent_doc_number] => 08943292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'System and method for memory array access with fast address decoder' [patent_app_type] => utility [patent_app_number] => 11/552817 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9915 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11552817 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/552817
System and method for memory array access with fast address decoder Oct 24, 2006 Issued
Array ( [id] => 5153116 [patent_doc_number] => 20070035998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Nonvolatile memory apparatus' [patent_app_type] => utility [patent_app_number] => 11/581690 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10254 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20070035998.pdf [firstpage_image] =>[orig_patent_app_number] => 11581690 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581690
Nonvolatile memory apparatus Oct 16, 2006 Abandoned
Array ( [id] => 4984214 [patent_doc_number] => 20070088773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Digital signal processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/549239 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088773.pdf [firstpage_image] =>[orig_patent_app_number] => 11549239 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549239
Digital signal processing apparatus Oct 12, 2006 Issued
Array ( [id] => 9187016 [patent_doc_number] => 08627002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Method to increase performance of non-contiguously written sectors' [patent_app_type] => utility [patent_app_number] => 11/549038 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2907 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11549038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549038
Method to increase performance of non-contiguously written sectors Oct 11, 2006 Issued
Array ( [id] => 4747277 [patent_doc_number] => 20080091879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Method and structure for interruting L2 cache live-lock occurrences' [patent_app_type] => utility [patent_app_number] => 11/548829 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4290 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091879.pdf [firstpage_image] =>[orig_patent_app_number] => 11548829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548829
Method and structure for interruting L2 cache live-lock occurrences Oct 11, 2006 Abandoned
Array ( [id] => 4747281 [patent_doc_number] => 20080091883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Load starvation detector and buster' [patent_app_type] => utility [patent_app_number] => 11/548820 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2309 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091883.pdf [firstpage_image] =>[orig_patent_app_number] => 11548820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548820
Load starvation detector and buster Oct 11, 2006 Abandoned
Array ( [id] => 4747299 [patent_doc_number] => 20080091901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Method for non-volatile memory with worst-case control data management' [patent_app_type] => utility [patent_app_number] => 11/549035 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 30170 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091901.pdf [firstpage_image] =>[orig_patent_app_number] => 11549035 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549035
Method for non-volatile memory with worst-case control data management Oct 11, 2006 Abandoned
Array ( [id] => 4747306 [patent_doc_number] => 20080091908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Speed selective table scan operation' [patent_app_type] => utility [patent_app_number] => 11/548889 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091908.pdf [firstpage_image] =>[orig_patent_app_number] => 11548889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548889
Speed selective table scan operation Oct 11, 2006 Issued
Array ( [id] => 4747307 [patent_doc_number] => 20080091909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'METHOD AND SYSTEM TO MANAGE VIRTUAL MACHINE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/548712 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8019 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091909.pdf [firstpage_image] =>[orig_patent_app_number] => 11548712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548712
METHOD AND SYSTEM TO MANAGE VIRTUAL MACHINE MEMORY Oct 11, 2006 Abandoned
Array ( [id] => 4747269 [patent_doc_number] => 20080091871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Non-volatile memory with worst-case control data management' [patent_app_type] => utility [patent_app_number] => 11/549040 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 30169 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091871.pdf [firstpage_image] =>[orig_patent_app_number] => 11549040 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549040
Non-volatile memory with worst-case control data management Oct 11, 2006 Abandoned
Array ( [id] => 5024701 [patent_doc_number] => 20070150668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/548603 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8550 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150668.pdf [firstpage_image] =>[orig_patent_app_number] => 11548603 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548603
MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE Oct 10, 2006 Abandoned
Array ( [id] => 4589763 [patent_doc_number] => 07831794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Memory card and host device thereof' [patent_app_type] => utility [patent_app_number] => 11/476853 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5922 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831794.pdf [firstpage_image] =>[orig_patent_app_number] => 11476853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/476853
Memory card and host device thereof Jun 28, 2006 Issued
Array ( [id] => 4996145 [patent_doc_number] => 20070011490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Information processing apparatus, and method of controlling operation of the same' [patent_app_type] => utility [patent_app_number] => 11/476738 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3797 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011490.pdf [firstpage_image] =>[orig_patent_app_number] => 11476738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/476738
Information processing apparatus, and method of controlling operation of the same Jun 28, 2006 Abandoned
Array ( [id] => 157681 [patent_doc_number] => 07685368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Methods and apparatus for removing data from a cache' [patent_app_type] => utility [patent_app_number] => 11/477022 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6088 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685368.pdf [firstpage_image] =>[orig_patent_app_number] => 11477022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477022
Methods and apparatus for removing data from a cache Jun 27, 2006 Issued
Array ( [id] => 5017597 [patent_doc_number] => 20070260806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Storage system' [patent_app_type] => utility [patent_app_number] => 11/475971 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12976 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260806.pdf [firstpage_image] =>[orig_patent_app_number] => 11475971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/475971
Storage system Jun 27, 2006 Issued
Array ( [id] => 7553157 [patent_doc_number] => 08065499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Methods and apparatus to implement parallel transactions' [patent_app_type] => utility [patent_app_number] => 11/475262 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065499.pdf [firstpage_image] =>[orig_patent_app_number] => 11475262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/475262
Methods and apparatus to implement parallel transactions Jun 26, 2006 Issued
Array ( [id] => 7692956 [patent_doc_number] => 20070016730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Cache consistency in a multiprocessor system with shared memory' [patent_app_type] => utility [patent_app_number] => 11/475844 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3879 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20070016730.pdf [firstpage_image] =>[orig_patent_app_number] => 11475844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/475844
Cache consistency in a multiprocessor system with shared memory Jun 26, 2006 Issued
Array ( [id] => 66392 [patent_doc_number] => 07765373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-27 [patent_title] => 'System for controlling use of a solid-state storage subsystem' [patent_app_type] => utility [patent_app_number] => 11/475386 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5617 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765373.pdf [firstpage_image] =>[orig_patent_app_number] => 11475386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/475386
System for controlling use of a solid-state storage subsystem Jun 26, 2006 Issued
Array ( [id] => 5114603 [patent_doc_number] => 20070198519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Methods and apparatus to implement parallel transactions' [patent_app_type] => utility [patent_app_number] => 11/475814 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198519.pdf [firstpage_image] =>[orig_patent_app_number] => 11475814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/475814
Methods and apparatus to implement parallel transactions Jun 26, 2006 Issued
Array ( [id] => 5200695 [patent_doc_number] => 20070300013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Storage system having transaction monitoring capability' [patent_app_type] => utility [patent_app_number] => 11/471558 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300013.pdf [firstpage_image] =>[orig_patent_app_number] => 11471558 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/471558
Storage system having transaction monitoring capability Jun 20, 2006 Abandoned
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