Evelyn Y. Pyla

Array ( [id] => 820001 [patent_doc_number] => 07412579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Secure memory controller' [patent_app_type] => utility [patent_app_number] => 11/027784 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3845 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412579.pdf [firstpage_image] =>[orig_patent_app_number] => 11027784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5633443 [patent_doc_number] => 20060149914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Systems and methods for allocating data structures to memories' [patent_app_type] => utility [patent_app_number] => 11/027759 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5052 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149914.pdf [firstpage_image] =>[orig_patent_app_number] => 11027759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 829165 [patent_doc_number] => 07404040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Packet data placement in a processor cache' [patent_app_type] => utility [patent_app_number] => 11/027971 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4507 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404040.pdf [firstpage_image] =>[orig_patent_app_number] => 11027971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8530590 [patent_doc_number] => 08307174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-06 [patent_title] => 'System and method for managing sessions and reallocating memory resources used for replication of data in a data storage environment' [patent_app_type] => utility [patent_app_number] => 10/953541 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7868 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10953541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 175562 [patent_doc_number] => 07660945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-09 [patent_title] => 'Methods and structure for limiting storage device write caching' [patent_app_type] => utility [patent_app_number] => 10/952981 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7493 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/660/07660945.pdf [firstpage_image] =>[orig_patent_app_number] => 10952981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 929603 [patent_doc_number] => 07315915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Non-volatile semiconductor memory device and electric device with the same' [patent_app_type] => utility [patent_app_number] => 10/950416 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4588 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315915.pdf [firstpage_image] =>[orig_patent_app_number] => 10950416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 825556 [patent_doc_number] => 07406570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Multisystem network, and device and method for access to data storage' [patent_app_type] => utility [patent_app_number] => 10/952389 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8798 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/406/07406570.pdf [firstpage_image] =>[orig_patent_app_number] => 10952389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5882553 [patent_doc_number] => 20060031636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Method of managing storage system to be managed by multiple managers' [patent_app_type] => utility [patent_app_number] => 10/938786 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7987 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20060031636.pdf [firstpage_image] =>[orig_patent_app_number] => 10938786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809319 [patent_doc_number] => 20060095674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Tracing instruction flow in an integrated processor' [patent_app_type] => utility [patent_app_number] => 10/925491 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095674.pdf [firstpage_image] =>[orig_patent_app_number] => 10925491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7167224 [patent_doc_number] => 20050086564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Multi-chip module and method for testing' [patent_app_type] => utility [patent_app_number] => 10/924565 [patent_app_country] => US [patent_app_date] => 2004-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086564.pdf [firstpage_image] =>[orig_patent_app_number] => 10924565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5592257 [patent_doc_number] => 20060041710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Option ROM code acquisition' [patent_app_type] => utility [patent_app_number] => 10/923905 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7341 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20060041710.pdf [firstpage_image] =>[orig_patent_app_number] => 10923905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 600287 [patent_doc_number] => 07437497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method and apparatus for encoding memory control signals to reduce pin count' [patent_app_type] => utility [patent_app_number] => 10/925173 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4541 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437497.pdf [firstpage_image] =>[orig_patent_app_number] => 10925173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809320 [patent_doc_number] => 20060095675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Three stage hybrid stack model' [patent_app_type] => utility [patent_app_number] => 10/925188 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1982 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095675.pdf [firstpage_image] =>[orig_patent_app_number] => 10925188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 321315 [patent_doc_number] => 07523285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Thermal memory control' [patent_app_type] => utility [patent_app_number] => 10/922737 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523285.pdf [firstpage_image] =>[orig_patent_app_number] => 10922737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7448784 [patent_doc_number] => 20040268053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method, device, and computer product for data storage control' [patent_app_type] => new [patent_app_number] => 10/914268 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4086 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268053.pdf [firstpage_image] =>[orig_patent_app_number] => 10914268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7087753 [patent_doc_number] => 20050007865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method for controlling non-volatile semiconductor memory system' [patent_app_type] => utility [patent_app_number] => 10/913865 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 20882 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007865.pdf [firstpage_image] =>[orig_patent_app_number] => 10913865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 418186 [patent_doc_number] => 07281116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes' [patent_app_type] => utility [patent_app_number] => 10/903200 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2413 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/281/07281116.pdf [firstpage_image] =>[orig_patent_app_number] => 10903200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 864033 [patent_doc_number] => 07373476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'System and method for configuration management of storage system' [patent_app_type] => utility [patent_app_number] => 10/889850 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10700 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/373/07373476.pdf [firstpage_image] =>[orig_patent_app_number] => 10889850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5896445 [patent_doc_number] => 20060004984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Virtual memory management system' [patent_app_type] => utility [patent_app_number] => 10/883360 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5820 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004984.pdf [firstpage_image] =>[orig_patent_app_number] => 10883360 [rel_patent_id] =>[rel_patent_doc_number] =>)