Evren Seven

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Array ( [id] => 19741408 [patent_doc_number] => 12218256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-04 [patent_title] => Trench MOS rectifier with termination structure [patent_app_type] => utility [patent_app_number] => 18/774563 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10687 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19705129 [patent_doc_number] => 12199177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => High-electron-mobility transistors with inactive gate blocks [patent_app_type] => utility [patent_app_number] => 18/769902 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19552888 [patent_doc_number] => 12136601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-05 [patent_title] => Single-sided embeddable capacitors for packaged semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/618869 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618869 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 19335800 [patent_doc_number] => 20240250230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => HIGHLY EFFICIENT MICRODEVICES [patent_app_type] => utility [patent_app_number] => 18/596923 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19239449 [patent_doc_number] => 20240196645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/583049 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583049 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 19384324 [patent_doc_number] => 20240274194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS [patent_app_type] => utility [patent_app_number] => 18/435434 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435434 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20139487 [patent_doc_number] => 20250246531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE WITH DIE INTERCONNECTS TERMINATING AT MULTIPLE METALLIZATION LAYERS IN A SUBSTRATE TO REDUCE SPACING REQUIREMENTS BETWEEN DIE INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 18/425447 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425447 [rel_patent_id] =>[rel_patent_doc_number] =>)

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