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Evren Seven

Examiner (ID: 787)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1095
Issued Applications
814
Pending Applications
111
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19907789 [patent_doc_number] => 12284819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-22 [patent_title] => Advanced low electrostatic field transistor [patent_app_type] => utility [patent_app_number] => 18/907921 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18907921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/907921
Advanced low electrostatic field transistor Oct 6, 2024 Issued
Array ( [id] => 19741408 [patent_doc_number] => 12218256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-04 [patent_title] => Trench MOS rectifier with termination structure [patent_app_type] => utility [patent_app_number] => 18/774563 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10687 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774563
Trench MOS rectifier with termination structure Jul 15, 2024 Issued
Array ( [id] => 19705129 [patent_doc_number] => 12199177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => High-electron-mobility transistors with inactive gate blocks [patent_app_type] => utility [patent_app_number] => 18/769902 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769902
High-electron-mobility transistors with inactive gate blocks Jul 10, 2024 Issued
Array ( [id] => 19552888 [patent_doc_number] => 12136601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-05 [patent_title] => Single-sided embeddable capacitors for packaged semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/618869 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618869
Single-sided embeddable capacitors for packaged semiconductor devices Mar 26, 2024 Issued
Array ( [id] => 19781655 [patent_doc_number] => 12230694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Method for making nanostructure transistors with source/drain trench contact liners [patent_app_type] => utility [patent_app_number] => 18/613557 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 4896 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613557 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613557
Method for making nanostructure transistors with source/drain trench contact liners Mar 21, 2024 Issued
Array ( [id] => 19335800 [patent_doc_number] => 20240250230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => HIGHLY EFFICIENT MICRODEVICES [patent_app_type] => utility [patent_app_number] => 18/596923 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596923
HIGHLY EFFICIENT MICRODEVICES Mar 5, 2024 Pending
Array ( [id] => 19239449 [patent_doc_number] => 20240196645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/583049 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583049
DISPLAY PANEL AND DISPLAY DEVICE Feb 20, 2024 Pending
Array ( [id] => 19853004 [patent_doc_number] => 20250098355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/444062 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444062
CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME Feb 15, 2024 Pending
Array ( [id] => 19548507 [patent_doc_number] => 20240365543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/435328 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435328
SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING SEMICONDUCTOR DEVICE Feb 6, 2024 Pending
Array ( [id] => 19386935 [patent_doc_number] => 20240276805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/435431 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435431
DISPLAY DEVICE Feb 6, 2024 Pending
Array ( [id] => 19206313 [patent_doc_number] => 20240178212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/435091 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435091
SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE Feb 6, 2024 Pending
Array ( [id] => 19384324 [patent_doc_number] => 20240274194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS [patent_app_type] => utility [patent_app_number] => 18/435434 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435434
MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS Feb 6, 2024 Pending
Array ( [id] => 20155160 [patent_doc_number] => 20250254998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => PIXEL STRUCTURE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/433458 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433458
PIXEL STRUCTURE AND DISPLAY DEVICE Feb 5, 2024 Pending
Array ( [id] => 19206401 [patent_doc_number] => 20240178300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/432694 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432694 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432694
Semiconductor device Feb 4, 2024 Issued
Array ( [id] => 19364440 [patent_doc_number] => 20240266474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/430747 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430747 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430747
SEMICONDUCTOR LIGHT EMITTING DEVICE Feb 1, 2024 Pending
Array ( [id] => 19364152 [patent_doc_number] => 20240266186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => STRESS MANAGEMENT FOR PRECISE SUBSTRATE -TO- SUBSTRATE BONDING [patent_app_type] => utility [patent_app_number] => 18/431860 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431860
STRESS MANAGEMENT FOR PRECISE SUBSTRATE -TO- SUBSTRATE BONDING Feb 1, 2024 Pending
Array ( [id] => 20065697 [patent_doc_number] => 20250203919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/431550 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431550
HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME Feb 1, 2024 Pending
Array ( [id] => 19337256 [patent_doc_number] => 20240251686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => LINEAR RESISTIVE ELEMENT AND PREPARATION METHOD [patent_app_type] => utility [patent_app_number] => 18/426367 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426367
LINEAR RESISTIVE ELEMENT AND PREPARATION METHOD Jan 29, 2024 Pending
Array ( [id] => 20139487 [patent_doc_number] => 20250246531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE WITH DIE INTERCONNECTS TERMINATING AT MULTIPLE METALLIZATION LAYERS IN A SUBSTRATE TO REDUCE SPACING REQUIREMENTS BETWEEN DIE INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 18/425447 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425447
INTEGRATED CIRCUIT (IC) PACKAGE WITH DIE INTERCONNECTS TERMINATING AT MULTIPLE METALLIZATION LAYERS IN A SUBSTRATE TO REDUCE SPACING REQUIREMENTS BETWEEN DIE INTERCONNECTS Jan 28, 2024 Pending
Array ( [id] => 20139446 [patent_doc_number] => 20250246490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => Electronic Component With Reduced Inductance [patent_app_type] => utility [patent_app_number] => 18/425298 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425298 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425298
Electronic Component With Reduced Inductance Jan 28, 2024 Pending
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