
Evren Seven
Examiner (ID: 9824, Phone: (571)270-5666 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1084 |
| Issued Applications | 810 |
| Pending Applications | 104 |
| Abandoned Applications | 202 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2949441
[patent_doc_number] => 05191544
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-02
[patent_title] => 'Personal computer enclosure with shielding'
[patent_app_type] => 1
[patent_app_number] => 7/538438
[patent_app_country] => US
[patent_app_date] => 1990-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3472
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/191/05191544.pdf
[firstpage_image] =>[orig_patent_app_number] => 538438
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/538438 | Personal computer enclosure with shielding | Jun 14, 1990 | Issued |
Array
(
[id] => 2758415
[patent_doc_number] => 05031138
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Improved ratio decoder for use in a non-restoring binary division circuit'
[patent_app_type] => 1
[patent_app_number] => 7/532729
[patent_app_country] => US
[patent_app_date] => 1990-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8009
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/031/05031138.pdf
[firstpage_image] =>[orig_patent_app_number] => 532729
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/532729 | Improved ratio decoder for use in a non-restoring binary division circuit | Jun 3, 1990 | Issued |
Array
(
[id] => 2810160
[patent_doc_number] => 05140542
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'Method and device for the arithmetical calculation of two-dimensional transforms'
[patent_app_type] => 1
[patent_app_number] => 7/531719
[patent_app_country] => US
[patent_app_date] => 1990-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1692
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/140/05140542.pdf
[firstpage_image] =>[orig_patent_app_number] => 531719
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/531719 | Method and device for the arithmetical calculation of two-dimensional transforms | May 31, 1990 | Issued |
Array
(
[id] => 2682351
[patent_doc_number] => 04984185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Portable computer having a battery voltage detecting circuit'
[patent_app_type] => 1
[patent_app_number] => 7/530458
[patent_app_country] => US
[patent_app_date] => 1990-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 2745
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/984/04984185.pdf
[firstpage_image] =>[orig_patent_app_number] => 530458
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/530458 | Portable computer having a battery voltage detecting circuit | May 29, 1990 | Issued |
Array
(
[id] => 2889838
[patent_doc_number] => 05109356
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Apparatus for computation of discrete Fourier transform using array parallel processor'
[patent_app_type] => 1
[patent_app_number] => 7/530099
[patent_app_country] => US
[patent_app_date] => 1990-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 7094
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 1031
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/109/05109356.pdf
[firstpage_image] =>[orig_patent_app_number] => 530099
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/530099 | Apparatus for computation of discrete Fourier transform using array parallel processor | May 28, 1990 | Issued |
Array
(
[id] => 2861596
[patent_doc_number] => 05089982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-18
[patent_title] => 'Two dimensional fast Fourier transform converter'
[patent_app_type] => 1
[patent_app_number] => 7/527959
[patent_app_country] => US
[patent_app_date] => 1990-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 7
[patent_no_of_words] => 6343
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/089/05089982.pdf
[firstpage_image] =>[orig_patent_app_number] => 527959
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/527959 | Two dimensional fast Fourier transform converter | May 23, 1990 | Issued |
| 07/521701 | PROCESSOR SUITABLE FOR RECURSIVE COMPUTATIONS | May 9, 1990 | Abandoned |
Array
(
[id] => 2718419
[patent_doc_number] => 05056054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-08
[patent_title] => 'Digital phase locked loop utilizing a multi-bit phase error input for control of a stepped clock generator'
[patent_app_type] => 1
[patent_app_number] => 7/518029
[patent_app_country] => US
[patent_app_date] => 1990-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 3564
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/056/05056054.pdf
[firstpage_image] =>[orig_patent_app_number] => 518029
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/518029 | Digital phase locked loop utilizing a multi-bit phase error input for control of a stepped clock generator | May 1, 1990 | Issued |
Array
(
[id] => 2823479
[patent_doc_number] => 05079734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Digital decimation filter'
[patent_app_type] => 1
[patent_app_number] => 7/516310
[patent_app_country] => US
[patent_app_date] => 1990-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3257
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/079/05079734.pdf
[firstpage_image] =>[orig_patent_app_number] => 516310
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/516310 | Digital decimation filter | Apr 29, 1990 | Issued |
Array
(
[id] => 2863677
[patent_doc_number] => 05126964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-30
[patent_title] => 'High performance bit-sliced multiplier circuit'
[patent_app_type] => 1
[patent_app_number] => 7/514719
[patent_app_country] => US
[patent_app_date] => 1990-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2855
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/126/05126964.pdf
[firstpage_image] =>[orig_patent_app_number] => 514719
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/514719 | High performance bit-sliced multiplier circuit | Apr 25, 1990 | Issued |
Array
(
[id] => 2823439
[patent_doc_number] => 05079732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Multi-functional electronic desk calculator'
[patent_app_type] => 1
[patent_app_number] => 7/513809
[patent_app_country] => US
[patent_app_date] => 1990-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 5720
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/079/05079732.pdf
[firstpage_image] =>[orig_patent_app_number] => 513809
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/513809 | Multi-functional electronic desk calculator | Apr 23, 1990 | Issued |
Array
(
[id] => 2810178
[patent_doc_number] => 05140543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'Apparatus for digitally processing audio signal'
[patent_app_type] => 1
[patent_app_number] => 7/510777
[patent_app_country] => US
[patent_app_date] => 1990-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 38
[patent_no_of_words] => 10865
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/140/05140543.pdf
[firstpage_image] =>[orig_patent_app_number] => 510777
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/510777 | Apparatus for digitally processing audio signal | Apr 17, 1990 | Issued |
| 07/509380 | APPARATUS FOR CALCULATING MATRICES | Apr 12, 1990 | Abandoned |
Array
(
[id] => 2889821
[patent_doc_number] => 05109355
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Data input apparatus having programmable key arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/506930
[patent_app_country] => US
[patent_app_date] => 1990-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4397
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/109/05109355.pdf
[firstpage_image] =>[orig_patent_app_number] => 506930
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/506930 | Data input apparatus having programmable key arrangement | Apr 9, 1990 | Issued |
Array
(
[id] => 2743630
[patent_doc_number] => 05051940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-24
[patent_title] => 'Data dependency collapsing hardware apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/504910
[patent_app_country] => US
[patent_app_date] => 1990-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 9567
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/051/05051940.pdf
[firstpage_image] =>[orig_patent_app_number] => 504910
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/504910 | Data dependency collapsing hardware apparatus | Apr 3, 1990 | Issued |
Array
(
[id] => 2756854
[patent_doc_number] => 05016207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-14
[patent_title] => 'High-speed digital filter processor including parallel paths for processing data, suitable for use in spatial filter image processing'
[patent_app_type] => 1
[patent_app_number] => 7/503424
[patent_app_country] => US
[patent_app_date] => 1990-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4585
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/016/05016207.pdf
[firstpage_image] =>[orig_patent_app_number] => 503424
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/503424 | High-speed digital filter processor including parallel paths for processing data, suitable for use in spatial filter image processing | Apr 2, 1990 | Issued |
Array
(
[id] => 2734563
[patent_doc_number] => 05058048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Normalizing pipelined floating point processing unit'
[patent_app_type] => 1
[patent_app_number] => 7/503819
[patent_app_country] => US
[patent_app_date] => 1990-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 6434
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/058/05058048.pdf
[firstpage_image] =>[orig_patent_app_number] => 503819
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/503819 | Normalizing pipelined floating point processing unit | Apr 1, 1990 | Issued |
| 07/505350 | SPECIAL CARRY SAVE ADDER FOR HIGH SPEED ITERATIVE DIVISION | Apr 1, 1990 | Abandoned |
Array
(
[id] => 2719252
[patent_doc_number] => 05018090
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Digital interpolation circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/493020
[patent_app_country] => US
[patent_app_date] => 1990-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2666
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/018/05018090.pdf
[firstpage_image] =>[orig_patent_app_number] => 493020
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/493020 | Digital interpolation circuitry | Mar 12, 1990 | Issued |
Array
(
[id] => 2694597
[patent_doc_number] => 05046179
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'Correlation computing device for image signal'
[patent_app_type] => 1
[patent_app_number] => 7/490420
[patent_app_country] => US
[patent_app_date] => 1990-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 5587
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/046/05046179.pdf
[firstpage_image] =>[orig_patent_app_number] => 490420
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/490420 | Correlation computing device for image signal | Mar 7, 1990 | Issued |