Evren Seven

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Array ( [id] => 20916924 [patent_doc_number] => 12713793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 18/435431 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 1111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19548507 [patent_doc_number] => 20240365543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/435328 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20155160 [patent_doc_number] => 20250254998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => PIXEL STRUCTURE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/433458 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433458 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20065697 [patent_doc_number] => 20250203919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/431550 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19364152 [patent_doc_number] => 20240266186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => STRESS MANAGEMENT FOR PRECISE SUBSTRATE -TO- SUBSTRATE BONDING [patent_app_type] => utility [patent_app_number] => 18/431860 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431860 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 19337256 [patent_doc_number] => 20240251686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => LINEAR RESISTIVE ELEMENT AND PREPARATION METHOD [patent_app_type] => utility [patent_app_number] => 18/426367 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19351292 [patent_doc_number] => 20240260256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/424919 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20139446 [patent_doc_number] => 20250246490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => Electronic Component With Reduced Inductance [patent_app_type] => utility [patent_app_number] => 18/425298 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20139492 [patent_doc_number] => 20250246536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => TRENCH CAPACITOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/425306 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20139487 [patent_doc_number] => 20250246531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE WITH DIE INTERCONNECTS TERMINATING AT MULTIPLE METALLIZATION LAYERS IN A SUBSTRATE TO REDUCE SPACING REQUIREMENTS BETWEEN DIE INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 18/425447 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425447 [rel_patent_id] =>[rel_patent_doc_number] =>)

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