Search

Evren Seven

Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1114
Issued Applications
823
Pending Applications
121
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16951711 [patent_doc_number] => 20210210403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => HEAT SPREADING PLATE HAVING ATLEAST ONE COOLING FIN METHOD FOR PRODUCING A HEAT SPREADING PLATE HAVING ATLEAST ONE COOLING FIN ELECTRONIC MODULE [patent_app_type] => utility [patent_app_number] => 15/999720 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999720 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/999720
HEAT SPREADING PLATE HAVING ATLEAST ONE COOLING FIN METHOD FOR PRODUCING A HEAT SPREADING PLATE HAVING ATLEAST ONE COOLING FIN ELECTRONIC MODULE Feb 8, 2017 Abandoned
Array ( [id] => 11824892 [patent_doc_number] => 20170213829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'SEMICONDUCTOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/427942 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7255 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427942 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/427942
Semiconductor structures Feb 7, 2017 Issued
Array ( [id] => 13769427 [patent_doc_number] => 10177063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Element chip and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/426181 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5869 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426181 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426181
Element chip and method for manufacturing the same Feb 6, 2017 Issued
Array ( [id] => 13005895 [patent_doc_number] => 10026618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Method for improving quality of spalled material layers [patent_app_type] => utility [patent_app_number] => 15/423130 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423130
Method for improving quality of spalled material layers Feb 1, 2017 Issued
Array ( [id] => 16896517 [patent_doc_number] => 11038080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from etching [patent_app_type] => utility [patent_app_number] => 15/422218 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 9157 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/422218
Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from etching Jan 31, 2017 Issued
Array ( [id] => 14521503 [patent_doc_number] => 10338002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-02 [patent_title] => Methods and systems for selecting recipe for defect inspection [patent_app_type] => utility [patent_app_number] => 15/411719 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4834 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411719
Methods and systems for selecting recipe for defect inspection Jan 19, 2017 Issued
Array ( [id] => 13293447 [patent_doc_number] => 10157924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Method and structure for FinFET devices [patent_app_type] => utility [patent_app_number] => 15/406362 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 6862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/406362
Method and structure for FinFET devices Jan 12, 2017 Issued
Array ( [id] => 14875429 [patent_doc_number] => 20190287956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => RECESSED SEMICONDUCTOR DIE IN A DIE STACK TO ACCOMODATE A COMPONENT [patent_app_type] => utility [patent_app_number] => 16/464665 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16464665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/464665
RECESSED SEMICONDUCTOR DIE IN A DIE STACK TO ACCOMODATE A COMPONENT Dec 29, 2016 Abandoned
Array ( [id] => 17254237 [patent_doc_number] => 11189737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Laminated body [patent_app_type] => utility [patent_app_number] => 16/065239 [patent_app_country] => US [patent_app_date] => 2016-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 12105 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16065239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/065239
Laminated body Dec 25, 2016 Issued
Array ( [id] => 11495356 [patent_doc_number] => 20170069541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS' [patent_app_type] => utility [patent_app_number] => 15/357201 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357201 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357201
METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS Nov 20, 2016 Abandoned
Array ( [id] => 14843567 [patent_doc_number] => 20190280184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => Piezoelectric Transmission and/or Reception Device, Vibration Sensor and Associated Method [patent_app_type] => utility [patent_app_number] => 16/345504 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16345504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/345504
Piezoelectric Transmission and/or Reception Device, Vibration Sensor and Associated Method Nov 17, 2016 Abandoned
Array ( [id] => 13558871 [patent_doc_number] => 20180330983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => MANUFACTURING METHOD OF SMOOTHING A SEMICONDUCTOR SURFACE [patent_app_type] => utility [patent_app_number] => 15/775924 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -45 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775924 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775924
Manufacturing method of smoothing a semiconductor surface Nov 14, 2016 Issued
Array ( [id] => 13559399 [patent_doc_number] => 20180331247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => SOLAR CELL PEPARATION METHOD [patent_app_type] => utility [patent_app_number] => 15/775923 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775923 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775923
SOLAR CELL PEPARATION METHOD Nov 10, 2016 Abandoned
Array ( [id] => 11460061 [patent_doc_number] => 20170053967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'DUMMY BOTTOM ELECTRODE IN INTERCONNECT TO REDUCE CMP DISHING' [patent_app_type] => utility [patent_app_number] => 15/345928 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345928 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345928
Dummy bottom electrode in interconnect to reduce CMP dishing Nov 7, 2016 Issued
Array ( [id] => 12033842 [patent_doc_number] => 20170323941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'HORIZONTAL NANOSHEET FETS AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/340775 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340775 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340775
Horizontal nanosheet FETs and methods of manufacturing the same Oct 31, 2016 Issued
Array ( [id] => 11446450 [patent_doc_number] => 20170047471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'THIN-FILM SEMICONDUCTOR OPTOELECTRONIC DEVICE WITH TEXTURED FRONT AND/OR BACK SURFACE PREPARED FROM TEMPLATE LAYER AND ETCHING' [patent_app_type] => utility [patent_app_number] => 15/340560 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8544 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340560
Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from template layer and etching Oct 31, 2016 Issued
Array ( [id] => 11952418 [patent_doc_number] => 20170256569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/340320 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340320
SEMICONDUCTOR DEVICE AND DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF Oct 31, 2016 Abandoned
Array ( [id] => 11608051 [patent_doc_number] => 20170125354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'CONDUCTIVE PLUG STRUCTURE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/340805 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340805 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340805
CONDUCTIVE PLUG STRUCTURE AND FABRICATION METHOD THEREOF Oct 31, 2016 Abandoned
Array ( [id] => 12692623 [patent_doc_number] => 20180122707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/339949 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339949 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/339949
Method for forming semiconductor device Oct 31, 2016 Issued
Array ( [id] => 14205339 [patent_doc_number] => 10269793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same [patent_app_type] => utility [patent_app_number] => 15/340783 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 8096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340783 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340783
Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same Oct 31, 2016 Issued
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