
Evren Seven
Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1114 |
| Issued Applications | 823 |
| Pending Applications | 121 |
| Abandoned Applications | 202 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11391797
[patent_doc_number] => 09553048
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-01-24
[patent_title] => 'Semiconductor device and manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/979662
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 6886
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 340
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979662
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/979662 | Semiconductor device and manufacturing method of semiconductor device | Dec 27, 2015 | Issued |
Array
(
[id] => 11286547
[patent_doc_number] => 09502407
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-11-22
[patent_title] => 'Integrating a planar field effect transistor (FET) with a vertical FET'
[patent_app_type] => utility
[patent_app_number] => 14/971105
[patent_app_country] => US
[patent_app_date] => 2015-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 3414
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971105
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/971105 | Integrating a planar field effect transistor (FET) with a vertical FET | Dec 15, 2015 | Issued |
Array
(
[id] => 11673836
[patent_doc_number] => 20170162559
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-08
[patent_title] => 'INTEGRATED VERTICAL SHARP TRANSISTOR AND FABRICATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/961317
[patent_app_country] => US
[patent_app_date] => 2015-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5227
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961317
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/961317 | INTEGRATED VERTICAL SHARP TRANSISTOR AND FABRICATION METHOD THEREOF | Dec 6, 2015 | Abandoned |
Array
(
[id] => 12059696
[patent_doc_number] => 20170336040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'LED LIGHT SOURCE FOR VEHICLE-MOUNTED HEADLIGHT'
[patent_app_type] => utility
[patent_app_number] => 15/534125
[patent_app_country] => US
[patent_app_date] => 2015-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5456
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15534125
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/534125 | LED LIGHT SOURCE FOR VEHICLE-MOUNTED HEADLIGHT | Dec 1, 2015 | Abandoned |
Array
(
[id] => 11483302
[patent_doc_number] => 09589856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-07
[patent_title] => 'Automatically adjusting baking process for low-k dielectric material'
[patent_app_type] => utility
[patent_app_number] => 14/949206
[patent_app_country] => US
[patent_app_date] => 2015-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2667
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949206
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/949206 | Automatically adjusting baking process for low-k dielectric material | Nov 22, 2015 | Issued |
Array
(
[id] => 10718356
[patent_doc_number] => 20160064503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'ELECTRONIC DEVICES AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/936442
[patent_app_country] => US
[patent_app_date] => 2015-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4644
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936442
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/936442 | ELECTRONIC DEVICES AND METHOD OF FABRICATING THE SAME | Nov 8, 2015 | Abandoned |
Array
(
[id] => 10709963
[patent_doc_number] => 20160056110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'METHOD OF FORMING A PATTERN'
[patent_app_type] => utility
[patent_app_number] => 14/929737
[patent_app_country] => US
[patent_app_date] => 2015-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5285
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14929737
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/929737 | Method of forming a pattern | Nov 1, 2015 | Issued |
Array
(
[id] => 11787648
[patent_doc_number] => 09397111
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-07-19
[patent_title] => 'Select gate transistor with single crystal silicon for three-dimensional memory'
[patent_app_type] => utility
[patent_app_number] => 14/927828
[patent_app_country] => US
[patent_app_date] => 2015-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 43
[patent_no_of_words] => 12723
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927828
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/927828 | Select gate transistor with single crystal silicon for three-dimensional memory | Oct 29, 2015 | Issued |
Array
(
[id] => 11307596
[patent_doc_number] => 09515000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-06
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/929252
[patent_app_country] => US
[patent_app_date] => 2015-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 14229
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14929252
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/929252 | Method for manufacturing semiconductor device | Oct 29, 2015 | Issued |
Array
(
[id] => 10753192
[patent_doc_number] => 20160099344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-07
[patent_title] => 'FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 14/928057
[patent_app_country] => US
[patent_app_date] => 2015-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7305
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928057
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/928057 | FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS | Oct 29, 2015 | Abandoned |
Array
(
[id] => 10802772
[patent_doc_number] => 20160148929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/926851
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5721
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926851
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926851 | Integrated circuit device | Oct 28, 2015 | Issued |
Array
(
[id] => 11608058
[patent_doc_number] => 20170125361
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/926880
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2925
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926880
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926880 | Semiconductor structure with anti-efuse device | Oct 28, 2015 | Issued |
Array
(
[id] => 11791710
[patent_doc_number] => 09401354
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-07-26
[patent_title] => 'Display panel having a reduced dead space'
[patent_app_type] => utility
[patent_app_number] => 14/926820
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4884
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926820
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926820 | Display panel having a reduced dead space | Oct 28, 2015 | Issued |
Array
(
[id] => 11551793
[patent_doc_number] => 09620655
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-04-11
[patent_title] => 'Laser foil trim approaches for foil-based metallization for solar cells'
[patent_app_type] => utility
[patent_app_number] => 14/927265
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 6352
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927265
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/927265 | Laser foil trim approaches for foil-based metallization for solar cells | Oct 28, 2015 | Issued |
Array
(
[id] => 11079212
[patent_doc_number] => 20160276176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-22
[patent_title] => 'REDUCTION OF DEFECTS IN WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/927283
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 8902
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927283
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/927283 | Reduction of defects in wafer level chip scale package (WLCSP) devices | Oct 28, 2015 | Issued |
Array
(
[id] => 10780165
[patent_doc_number] => 20160126321
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-05
[patent_title] => 'SUBSTRATE WITH SILICON CARBIDE FILM, METHOD FOR PRODUCING SUBSTRATE WITH SILICON CARBIDE FILM, AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/926914
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8787
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926914
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926914 | Substrate with silicon carbide film, method for producing substrate with silicon carbide film, and semiconductor device | Oct 28, 2015 | Issued |
Array
(
[id] => 10779954
[patent_doc_number] => 20160126110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-05
[patent_title] => 'METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 14/927457
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4745
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927457
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/927457 | METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT | Oct 28, 2015 | Abandoned |
Array
(
[id] => 10802769
[patent_doc_number] => 20160148926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/926888
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5874
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926888
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926888 | Integrated circuit device | Oct 28, 2015 | Issued |
Array
(
[id] => 11862159
[patent_doc_number] => 09741853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Stress memorization techniques for transistor devices'
[patent_app_type] => utility
[patent_app_number] => 14/926897
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 6123
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926897
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926897 | Stress memorization techniques for transistor devices | Oct 28, 2015 | Issued |
Array
(
[id] => 10787577
[patent_doc_number] => 20160133733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'POWER SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/926962
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3160
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926962
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926962 | POWER SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF | Oct 28, 2015 | Abandoned |