
Evren Seven
Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1114 |
| Issued Applications | 823 |
| Pending Applications | 121 |
| Abandoned Applications | 202 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9318877
[patent_doc_number] => 20140051215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'METHOD FOR MAKING THIN FILM TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 14/059753
[patent_app_country] => US
[patent_app_date] => 2013-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5737
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059753
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/059753 | Method for making thin film transistor | Oct 21, 2013 | Issued |
Array
(
[id] => 10219889
[patent_doc_number] => 20150104882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'FABRICATION METHOD FOR HIGH-DENSITY MRAM USING THIN HARD MASK'
[patent_app_type] => utility
[patent_app_number] => 14/051327
[patent_app_country] => US
[patent_app_date] => 2013-10-10
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051327
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/051327 | Fabrication method for high-density MRAM using thin hard mask | Oct 9, 2013 | Issued |
Array
(
[id] => 10537883
[patent_doc_number] => 09263520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Facilitating fabricating gate-all-around nanowire field-effect transistors'
[patent_app_type] => utility
[patent_app_number] => 14/050494
[patent_app_country] => US
[patent_app_date] => 2013-10-10
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050494
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/050494 | Facilitating fabricating gate-all-around nanowire field-effect transistors | Oct 9, 2013 | Issued |
Array
(
[id] => 10410053
[patent_doc_number] => 20150295062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-15
[patent_title] => 'VERTICALLY MOVABLE GATE FIELD EFFECT TRANSISTOR (VMGFET) ON A SILICON-ON-INSULATOR (SOI) WAFER AND METHOD OF FORMING A VMGFET'
[patent_app_type] => utility
[patent_app_number] => 14/435303
[patent_app_country] => US
[patent_app_date] => 2013-10-10
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435303
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/435303 | Vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer and method of forming a VMGFET | Oct 9, 2013 | Issued |
Array
(
[id] => 10208888
[patent_doc_number] => 20150093878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'FINFET FABRICATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/044533
[patent_app_country] => US
[patent_app_date] => 2013-10-02
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044533
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/044533 | FinFET fabrication method | Oct 1, 2013 | Issued |
Array
(
[id] => 10208899
[patent_doc_number] => 20150093889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 14/044376
[patent_app_country] => US
[patent_app_date] => 2013-10-02
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044376
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/044376 | METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS | Oct 1, 2013 | Abandoned |
Array
(
[id] => 10394835
[patent_doc_number] => 20150279842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/435453
[patent_app_country] => US
[patent_app_date] => 2013-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435453
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/435453 | Semiconductor device and method for manufacturing the same | Oct 1, 2013 | Issued |
Array
(
[id] => 10060064
[patent_doc_number] => 09099428
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-04
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/043058
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/043058 | Method for manufacturing semiconductor device | Sep 30, 2013 | Issued |
Array
(
[id] => 10060064
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/043058 | Method for manufacturing semiconductor device | Sep 30, 2013 | Issued |
Array
(
[id] => 10208887
[patent_doc_number] => 20150093877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE BY STOPPING PLANARIZATION OF INSULATING MATERIAL ON FINS'
[patent_app_type] => utility
[patent_app_number] => 14/042997
[patent_app_country] => US
[patent_app_date] => 2013-10-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/042997 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE BY STOPPING PLANARIZATION OF INSULATING MATERIAL ON FINS | Sep 30, 2013 | Abandoned |
Array
(
[id] => 10060064
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Array
(
[id] => 10208871
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[patent_country] => US
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[patent_issue_date] => 2015-04-02
[patent_title] => 'METHOD FOR THE FORMATION OF CMOS TRANSISTORS'
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Array
(
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Array
(
[id] => 9280918
[patent_doc_number] => 20140030886
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[patent_issue_date] => 2014-01-30
[patent_title] => 'METHOD FOR FORMING COPPER WIRING'
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Array
(
[id] => 10073731
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Array
(
[id] => 10551242
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[patent_issue_date] => 2016-03-01
[patent_title] => 'Masking process and structures formed thereby'
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Array
(
[id] => 10336622
[patent_doc_number] => 20150221627
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[patent_title] => 'MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/576068 | MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER | Sep 24, 2013 | Abandoned |
Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/028799 | Chemical dielectric formation for semiconductor device fabrication | Sep 16, 2013 | Issued |