Search

Evren Seven

Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1114
Issued Applications
823
Pending Applications
121
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9318877 [patent_doc_number] => 20140051215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'METHOD FOR MAKING THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/059753 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5737 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059753 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059753
Method for making thin film transistor Oct 21, 2013 Issued
Array ( [id] => 10219889 [patent_doc_number] => 20150104882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'FABRICATION METHOD FOR HIGH-DENSITY MRAM USING THIN HARD MASK' [patent_app_type] => utility [patent_app_number] => 14/051327 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4522 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051327 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051327
Fabrication method for high-density MRAM using thin hard mask Oct 9, 2013 Issued
Array ( [id] => 10537883 [patent_doc_number] => 09263520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Facilitating fabricating gate-all-around nanowire field-effect transistors' [patent_app_type] => utility [patent_app_number] => 14/050494 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 7305 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050494 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050494
Facilitating fabricating gate-all-around nanowire field-effect transistors Oct 9, 2013 Issued
Array ( [id] => 10410053 [patent_doc_number] => 20150295062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'VERTICALLY MOVABLE GATE FIELD EFFECT TRANSISTOR (VMGFET) ON A SILICON-ON-INSULATOR (SOI) WAFER AND METHOD OF FORMING A VMGFET' [patent_app_type] => utility [patent_app_number] => 14/435303 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/435303
Vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer and method of forming a VMGFET Oct 9, 2013 Issued
Array ( [id] => 10208888 [patent_doc_number] => 20150093878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'FINFET FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/044533 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044533 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044533
FinFET fabrication method Oct 1, 2013 Issued
Array ( [id] => 10208899 [patent_doc_number] => 20150093889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/044376 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044376
METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS Oct 1, 2013 Abandoned
Array ( [id] => 10394835 [patent_doc_number] => 20150279842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/435453 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435453 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/435453
Semiconductor device and method for manufacturing the same Oct 1, 2013 Issued
Array ( [id] => 10060064 [patent_doc_number] => 09099428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/043058 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 23386 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043058
Method for manufacturing semiconductor device Sep 30, 2013 Issued
Array ( [id] => 10060064 [patent_doc_number] => 09099428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/043058 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 23386 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043058
Method for manufacturing semiconductor device Sep 30, 2013 Issued
Array ( [id] => 10208887 [patent_doc_number] => 20150093877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE BY STOPPING PLANARIZATION OF INSULATING MATERIAL ON FINS' [patent_app_type] => utility [patent_app_number] => 14/042997 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042997
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE BY STOPPING PLANARIZATION OF INSULATING MATERIAL ON FINS Sep 30, 2013 Abandoned
Array ( [id] => 10060064 [patent_doc_number] => 09099428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/043058 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 23386 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043058
Method for manufacturing semiconductor device Sep 30, 2013 Issued
Array ( [id] => 10208871 [patent_doc_number] => 20150093861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHOD FOR THE FORMATION OF CMOS TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/042884 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042884 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042884
METHOD FOR THE FORMATION OF CMOS TRANSISTORS Sep 30, 2013 Abandoned
Array ( [id] => 10060064 [patent_doc_number] => 09099428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/043058 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 23386 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043058
Method for manufacturing semiconductor device Sep 30, 2013 Issued
Array ( [id] => 9280918 [patent_doc_number] => 20140030886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'METHOD FOR FORMING COPPER WIRING' [patent_app_type] => utility [patent_app_number] => 14/042198 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042198
METHOD FOR FORMING COPPER WIRING Sep 29, 2013 Abandoned
Array ( [id] => 10073731 [patent_doc_number] => 09112097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Alignment for metallization' [patent_app_type] => utility [patent_app_number] => 14/040177 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14040177 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/040177
Alignment for metallization Sep 26, 2013 Issued
Array ( [id] => 10551242 [patent_doc_number] => 09275873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Masking process and structures formed thereby' [patent_app_type] => utility [patent_app_number] => 14/038355 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3525 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038355 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038355
Masking process and structures formed thereby Sep 25, 2013 Issued
Array ( [id] => 10336622 [patent_doc_number] => 20150221627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER' [patent_app_type] => utility [patent_app_number] => 14/576068 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576068
MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER Sep 24, 2013 Abandoned
Array ( [id] => 10202143 [patent_doc_number] => 20150087131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'METHOD FOR PROCESSING A CHIP' [patent_app_type] => utility [patent_app_number] => 14/032223 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14032223 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/032223
METHOD FOR PROCESSING A CHIP Sep 19, 2013 Abandoned
Array ( [id] => 9882405 [patent_doc_number] => 08969169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-03 [patent_title] => 'DRAM MIM capacitor using non-noble electrodes' [patent_app_type] => utility [patent_app_number] => 14/033326 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/033326
DRAM MIM capacitor using non-noble electrodes Sep 19, 2013 Issued
Array ( [id] => 10016071 [patent_doc_number] => 09059092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Chemical dielectric formation for semiconductor device fabrication' [patent_app_type] => utility [patent_app_number] => 14/028799 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028799 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/028799
Chemical dielectric formation for semiconductor device fabrication Sep 16, 2013 Issued
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