
Evren Seven
Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1114 |
| Issued Applications | 823 |
| Pending Applications | 121 |
| Abandoned Applications | 202 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8963635
[patent_doc_number] => 20130203237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-08
[patent_title] => 'CUTTING METHOD FOR DEVICE WAFER'
[patent_app_type] => utility
[patent_app_number] => 13/754386
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2892
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754386
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754386 | CUTTING METHOD FOR DEVICE WAFER | Jan 29, 2013 | Abandoned |
Array
(
[id] => 9957851
[patent_doc_number] => 09006055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-14
[patent_title] => 'High voltage FINFET structure'
[patent_app_type] => utility
[patent_app_number] => 13/754065
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754065
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754065 | High voltage FINFET structure | Jan 29, 2013 | Issued |
Array
(
[id] => 8950710
[patent_doc_number] => 20130196491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-01
[patent_title] => 'METHOD OF PREVENTING DOPANT FROM DIFFUSING INTO ATMOSPHERE IN A BICMOS PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/753983
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 1905
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753983
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753983 | METHOD OF PREVENTING DOPANT FROM DIFFUSING INTO ATMOSPHERE IN A BICMOS PROCESS | Jan 29, 2013 | Abandoned |
Array
(
[id] => 9777818
[patent_doc_number] => 08853023
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-07
[patent_title] => 'Method for stressing a thin pattern and transistor fabrication method incorporating said method'
[patent_app_type] => utility
[patent_app_number] => 13/753436
[patent_app_country] => US
[patent_app_date] => 2013-01-29
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753436
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753436 | Method for stressing a thin pattern and transistor fabrication method incorporating said method | Jan 28, 2013 | Issued |
Array
(
[id] => 9634925
[patent_doc_number] => 20140213034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'METHOD FOR FORMING ISOLATION STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/752408
[patent_app_country] => US
[patent_app_date] => 2013-01-29
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/752408 | METHOD FOR FORMING ISOLATION STRUCTURE | Jan 28, 2013 | Abandoned |
Array
(
[id] => 9703778
[patent_doc_number] => 08828839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-09
[patent_title] => 'Methods for fabricating electrically-isolated finFET semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/753269
[patent_app_country] => US
[patent_app_date] => 2013-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753269
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753269 | Methods for fabricating electrically-isolated finFET semiconductor devices | Jan 28, 2013 | Issued |
Array
(
[id] => 10016054
[patent_doc_number] => 09059075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-16
[patent_title] => 'Selective gallium nitride regrowth on (100) silicon'
[patent_app_type] => utility
[patent_app_number] => 13/751799
[patent_app_country] => US
[patent_app_date] => 2013-01-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751799
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/751799 | Selective gallium nitride regrowth on (100) silicon | Jan 27, 2013 | Issued |
Array
(
[id] => 10440515
[patent_doc_number] => 20150325527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'RADIUSED ALIGNMENT POST FOR SUBSTRATE MATERIAL'
[patent_app_type] => utility
[patent_app_number] => 14/764005
[patent_app_country] => US
[patent_app_date] => 2013-01-28
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/764005 | RADIUSED ALIGNMENT POST FOR SUBSTRATE MATERIAL | Jan 27, 2013 | Abandoned |
Array
(
[id] => 9799134
[patent_doc_number] => 20150011079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-08
[patent_title] => 'METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER'
[patent_app_type] => utility
[patent_app_number] => 14/373720
[patent_app_country] => US
[patent_app_date] => 2013-01-21
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/373720 | METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER | Jan 20, 2013 | Abandoned |
Array
(
[id] => 8821634
[patent_doc_number] => 20130122680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'RESISTOR STRUCTURE FOR A NON-VOLATILE MEMORY DEVICE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/739283
[patent_app_country] => US
[patent_app_date] => 2013-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/739283 | Resistor structure for a non-volatile memory device and method | Jan 10, 2013 | Issued |
Array
(
[id] => 13857383
[patent_doc_number] => 10190403
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => System and method for predicting and visualizing drilling events
[patent_app_type] => utility
[patent_app_number] => 14/655284
[patent_app_country] => US
[patent_app_date] => 2013-01-03
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14655284
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/655284 | System and method for predicting and visualizing drilling events | Jan 2, 2013 | Issued |
Array
(
[id] => 9299668
[patent_doc_number] => 08647894
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-11
[patent_title] => 'Method for generating graphene structures'
[patent_app_type] => utility
[patent_app_number] => 13/726834
[patent_app_country] => US
[patent_app_date] => 2012-12-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/726834 | Method for generating graphene structures | Dec 25, 2012 | Issued |
Array
(
[id] => 9951662
[patent_doc_number] => 09000453
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-07
[patent_title] => 'Electrostatic discharge protection for electrical components, devices including such protection and methods for making the same'
[patent_app_type] => utility
[patent_app_number] => 13/724713
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/724713 | Electrostatic discharge protection for electrical components, devices including such protection and methods for making the same | Dec 20, 2012 | Issued |
Array
(
[id] => 9850147
[patent_doc_number] => 08951875
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[patent_issue_date] => 2015-02-10
[patent_title] => 'Semiconductor structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/710078 | Semiconductor structure | Dec 9, 2012 | Issued |
Array
(
[id] => 10440672
[patent_doc_number] => 20150325684
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[patent_title] => 'MANUFACTURING METHOD OF N-TYPE MOSFET'
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Array
(
[id] => 9799125
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/373628 | METHOD FOR MANUFACTURING P-TYPE MOSFET | Dec 6, 2012 | Abandoned |
Array
(
[id] => 10000718
[patent_doc_number] => 09044793
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[patent_kind] => B2
[patent_issue_date] => 2015-06-02
[patent_title] => 'Method for cleaning film formation apparatus and method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/680187
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/680187 | Method for cleaning film formation apparatus and method for manufacturing semiconductor device | Nov 18, 2012 | Issued |
Array
(
[id] => 9491160
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[patent_issue_date] => 2014-05-22
[patent_title] => 'GATE INSULATOR UNIFORMITY'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'LIGHT EMITTING DEVICE AND LIGHT-EMITTING SYSTEM INCLUDING THE SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/675603 | Light emitting device and light-emitting system including the same | Nov 12, 2012 | Issued |
Array
(
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[patent_title] => 'PACKAGE HAVING STACKED MEMORY DIES WITH SERIALLY CONNECTED BUFFER DIES'
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[patent_app_number] => 13/675163
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/675163 | PACKAGE HAVING STACKED MEMORY DIES WITH SERIALLY CONNECTED BUFFER DIES | Nov 12, 2012 | Abandoned |