Search

Evren Seven

Examiner (ID: 9824, Phone: (571)270-5666 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1084
Issued Applications
810
Pending Applications
104
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2979342 [patent_doc_number] => 05258945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Method and apparatus for generating multiples of BCD number' [patent_app_type] => 1 [patent_app_number] => 7/814407 [patent_app_country] => US [patent_app_date] => 1991-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7166 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258945.pdf [firstpage_image] =>[orig_patent_app_number] => 814407 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/814407
Method and apparatus for generating multiples of BCD number Dec 22, 1991 Issued
07/807238 OPERATIONAL CIRCUIT DEVICE Dec 15, 1991 Abandoned
Array ( [id] => 2904998 [patent_doc_number] => 05241493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Floating point arithmetic unit with size efficient pipelined multiply-add architecture' [patent_app_type] => 1 [patent_app_number] => 7/807697 [patent_app_country] => US [patent_app_date] => 1991-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3479 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241493.pdf [firstpage_image] =>[orig_patent_app_number] => 807697 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/807697
Floating point arithmetic unit with size efficient pipelined multiply-add architecture Dec 15, 1991 Issued
Array ( [id] => 2942493 [patent_doc_number] => 05233550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Adaptive balance filter' [patent_app_type] => 1 [patent_app_number] => 7/807167 [patent_app_country] => US [patent_app_date] => 1991-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2413 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233550.pdf [firstpage_image] =>[orig_patent_app_number] => 807167 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/807167
Adaptive balance filter Dec 12, 1991 Issued
07/806778 METHOD AND PROCESSOR FOR HIGH-SPEED CONVERGENCE FACTOR DETERMINATION Dec 11, 1991 Abandoned
Array ( [id] => 2928773 [patent_doc_number] => 05206828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Special carry save adder for high speed iterative division' [patent_app_type] => 1 [patent_app_number] => 7/806820 [patent_app_country] => US [patent_app_date] => 1991-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2692 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206828.pdf [firstpage_image] =>[orig_patent_app_number] => 806820 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/806820
Special carry save adder for high speed iterative division Dec 5, 1991 Issued
Array ( [id] => 2998000 [patent_doc_number] => 05267185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Apparatus for calculating matrices' [patent_app_type] => 1 [patent_app_number] => 7/798939 [patent_app_country] => US [patent_app_date] => 1991-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6042 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/267/05267185.pdf [firstpage_image] =>[orig_patent_app_number] => 798939 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/798939
Apparatus for calculating matrices Nov 26, 1991 Issued
Array ( [id] => 3067414 [patent_doc_number] => 05339251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Apparatus for adaptively tuning to a received periodic signal' [patent_app_type] => 1 [patent_app_number] => 7/796318 [patent_app_country] => US [patent_app_date] => 1991-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3109 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339251.pdf [firstpage_image] =>[orig_patent_app_number] => 796318 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/796318
Apparatus for adaptively tuning to a received periodic signal Nov 21, 1991 Issued
Array ( [id] => 3455525 [patent_doc_number] => 05420815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Digital multiplication and accumulation system' [patent_app_type] => 1 [patent_app_number] => 7/783837 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4243 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420815.pdf [firstpage_image] =>[orig_patent_app_number] => 783837 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/783837
Digital multiplication and accumulation system Oct 28, 1991 Issued
Array ( [id] => 2948076 [patent_doc_number] => 05260897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Signal processing circuit' [patent_app_type] => 1 [patent_app_number] => 7/783907 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3153 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260897.pdf [firstpage_image] =>[orig_patent_app_number] => 783907 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/783907
Signal processing circuit Oct 28, 1991 Issued
Array ( [id] => 3092036 [patent_doc_number] => 05285185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Dual-coded data comparator' [patent_app_type] => 1 [patent_app_number] => 7/784547 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5375 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285185.pdf [firstpage_image] =>[orig_patent_app_number] => 784547 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/784547
Dual-coded data comparator Oct 28, 1991 Issued
Array ( [id] => 2931312 [patent_doc_number] => 05235537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Digital processor for two\'s complement computations' [patent_app_type] => 1 [patent_app_number] => 7/768887 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10079 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235537.pdf [firstpage_image] =>[orig_patent_app_number] => 768887 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/768887
Digital processor for two's complement computations Oct 28, 1991 Issued
Array ( [id] => 2942509 [patent_doc_number] => 05233551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Radix-12 DFT/FFT building block' [patent_app_type] => 1 [patent_app_number] => 7/779778 [patent_app_country] => US [patent_app_date] => 1991-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7323 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233551.pdf [firstpage_image] =>[orig_patent_app_number] => 779778 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/779778
Radix-12 DFT/FFT building block Oct 20, 1991 Issued
Array ( [id] => 3091934 [patent_doc_number] => 05280439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Apparatus for determining booth recoder input control signals' [patent_app_type] => 1 [patent_app_number] => 7/774674 [patent_app_country] => US [patent_app_date] => 1991-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 7869 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280439.pdf [firstpage_image] =>[orig_patent_app_number] => 774674 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/774674
Apparatus for determining booth recoder input control signals Oct 10, 1991 Issued
Array ( [id] => 2979214 [patent_doc_number] => 05258939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Fold and decimate filter architecture' [patent_app_type] => 1 [patent_app_number] => 7/774628 [patent_app_country] => US [patent_app_date] => 1991-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4586 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258939.pdf [firstpage_image] =>[orig_patent_app_number] => 774628 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/774628
Fold and decimate filter architecture Oct 9, 1991 Issued
Array ( [id] => 3091953 [patent_doc_number] => 05280440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Parallel adding circuit using 3.times.3 matrix of .+-. quinary number representation' [patent_app_type] => 1 [patent_app_number] => 7/773727 [patent_app_country] => US [patent_app_date] => 1991-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10168 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280440.pdf [firstpage_image] =>[orig_patent_app_number] => 773727 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/773727
Parallel adding circuit using 3.times.3 matrix of .+-. quinary number representation Oct 8, 1991 Issued
Array ( [id] => 2810196 [patent_doc_number] => 05140544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Divide-by-five divider' [patent_app_type] => 1 [patent_app_number] => 7/772498 [patent_app_country] => US [patent_app_date] => 1991-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3365 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140544.pdf [firstpage_image] =>[orig_patent_app_number] => 772498 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/772498
Divide-by-five divider Oct 6, 1991 Issued
Array ( [id] => 2902526 [patent_doc_number] => 05210712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Waveform shaping circuit and digital signal analyzing apparatus using the same' [patent_app_type] => 1 [patent_app_number] => 7/764158 [patent_app_country] => US [patent_app_date] => 1991-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 8367 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210712.pdf [firstpage_image] =>[orig_patent_app_number] => 764158 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/764158
Waveform shaping circuit and digital signal analyzing apparatus using the same Sep 19, 1991 Issued
Array ( [id] => 2908455 [patent_doc_number] => 05245563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Fast control for round unit' [patent_app_type] => 1 [patent_app_number] => 7/763127 [patent_app_country] => US [patent_app_date] => 1991-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2415 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/245/05245563.pdf [firstpage_image] =>[orig_patent_app_number] => 763127 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/763127
Fast control for round unit Sep 19, 1991 Issued
Array ( [id] => 2931288 [patent_doc_number] => 05235536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Absolute difference processor element processing unit, and processor' [patent_app_type] => 1 [patent_app_number] => 7/762348 [patent_app_country] => US [patent_app_date] => 1991-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5946 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235536.pdf [firstpage_image] =>[orig_patent_app_number] => 762348 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/762348
Absolute difference processor element processing unit, and processor Sep 18, 1991 Issued
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