Evren Seven

Array ( [id] => 8516330 [patent_doc_number] => 20120315738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/493443 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8617806 [patent_doc_number] => 20130023118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'METHOD FOR FORMING PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/493321 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8022 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9468916 [patent_doc_number] => 08722546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Method for forming silicon-containing dielectric film by cyclic deposition with side wall coverage control' [patent_app_type] => utility [patent_app_number] => 13/493897 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8522860 [patent_doc_number] => 20120322268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'METHOD OF FORMING A PATTERN' [patent_app_type] => utility [patent_app_number] => 13/493146 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5247 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9482997 [patent_doc_number] => 08728947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Gas cluster ion beam process for opening conformal layer in a high aspect ratio contact via' [patent_app_type] => utility [patent_app_number] => 13/492094 [patent_app_country] => US [patent_app_date] => 2012-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 16963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13492094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9191578 [patent_doc_number] => 20130330893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'INTEGRATING FORMATION OF A REPLACEMENT GATE TRANSISTOR AND A NON-VOLATILE MEMORY CELL USING A HIGH-K DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 13/491771 [patent_app_country] => US [patent_app_date] => 2012-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13491771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8901359 [patent_doc_number] => 20130168862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'METHOD OF MANUFACTURING BARRIER LAYER PATTERNS OF A SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE OF BARRIER LAYER PATTERNS OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/492059 [patent_app_country] => US [patent_app_date] => 2012-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3642 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13492059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9355150 [patent_doc_number] => 08673683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Graphene field effect transistor' [patent_app_type] => utility [patent_app_number] => 13/492131 [patent_app_country] => US [patent_app_date] => 2012-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 8083 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13492131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9496370 [patent_doc_number] => 08735182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Method for detecting embedded voids in a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 13/490828 [patent_app_country] => US [patent_app_date] => 2012-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7360 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13490828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9530033 [patent_doc_number] => 08753904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Method and system for semiconductor device pattern loading effect characterization' [patent_app_type] => utility [patent_app_number] => 13/491252 [patent_app_country] => US [patent_app_date] => 2012-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13491252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8516318 [patent_doc_number] => 20120315726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/491055 [patent_app_country] => US [patent_app_date] => 2012-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5502 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13491055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10001266 [patent_doc_number] => 09045343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Carbon nanotube foams with controllable mechanical properties' [patent_app_type] => utility [patent_app_number] => 13/491014 [patent_app_country] => US [patent_app_date] => 2012-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 12752 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13491014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8509704 [patent_doc_number] => 20120309112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/489206 [patent_app_country] => US [patent_app_date] => 2012-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9796 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13489206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8932520 [patent_doc_number] => 08492219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 13/487295 [patent_app_country] => US [patent_app_date] => 2012-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 10200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8508037 [patent_doc_number] => 20120307445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'PRINTED CIRCUIT BOARD (PCB) INCLUDING A WIRE PATTERN, SEMICONDUCTOR PACKAGE INCLUDING THE PCB, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE PCB, AND METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/486235 [patent_app_country] => US [patent_app_date] => 2012-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7354 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13486235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8502585 [patent_doc_number] => 20120301993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/486843 [patent_app_country] => US [patent_app_date] => 2012-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7588 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13486843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8417186 [patent_doc_number] => 20120244686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/486169 [patent_app_country] => US [patent_app_date] => 2012-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13259 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13486169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10932621 [patent_doc_number] => 20140335642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'METHOD FOR MANUFACTURING ORGANIC SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 14/354756 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6433 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14354756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9026413 [patent_doc_number] => 08535994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Thin-film transistor array device manufacturing method' [patent_app_type] => utility [patent_app_number] => 13/476460 [patent_app_country] => US [patent_app_date] => 2012-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 16332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13476460 [rel_patent_id] =>[rel_patent_doc_number] =>)