Search

Evren Seven

Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1114
Issued Applications
823
Pending Applications
121
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7815217 [patent_doc_number] => 20120061837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/230106 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1853 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061837.pdf [firstpage_image] =>[orig_patent_app_number] => 13230106 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/230106
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Sep 11, 2011 Abandoned
Array ( [id] => 8846133 [patent_doc_number] => 08455312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits' [patent_app_type] => utility [patent_app_number] => 13/199816 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4603 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 435 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13199816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/199816
Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits Sep 11, 2011 Issued
Array ( [id] => 8042443 [patent_doc_number] => 20120070957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'AIR GAP FORMATION' [patent_app_type] => utility [patent_app_number] => 13/229673 [patent_app_country] => US [patent_app_date] => 2011-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20120070957.pdf [firstpage_image] =>[orig_patent_app_number] => 13229673 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229673
Air gap formation Sep 9, 2011 Issued
Array ( [id] => 8172678 [patent_doc_number] => 20120108035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Method of Fabricating Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/228966 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8210 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20120108035.pdf [firstpage_image] =>[orig_patent_app_number] => 13228966 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228966
Method of Fabricating Semiconductor Device Sep 8, 2011 Abandoned
Array ( [id] => 7818068 [patent_doc_number] => 20120064688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/229570 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3623 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064688.pdf [firstpage_image] =>[orig_patent_app_number] => 13229570 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229570
METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR Sep 8, 2011 Abandoned
Array ( [id] => 8846113 [patent_doc_number] => 08455292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Deposition of germanium film' [patent_app_type] => utility [patent_app_number] => 13/229440 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2632 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13229440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229440
Deposition of germanium film Sep 8, 2011 Issued
Array ( [id] => 7818060 [patent_doc_number] => 20120064680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/228867 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064680.pdf [firstpage_image] =>[orig_patent_app_number] => 13228867 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228867
METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME Sep 8, 2011 Abandoned
Array ( [id] => 7818051 [patent_doc_number] => 20120064671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD FOR PRODUCING CHIP ELEMENTS EQUIPPED WITH WIRE INSERTION GROOVES' [patent_app_type] => utility [patent_app_number] => 13/229021 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2370 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064671.pdf [firstpage_image] =>[orig_patent_app_number] => 13229021 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229021
Method for producing chip elements equipped with wire insertion grooves Sep 8, 2011 Issued
Array ( [id] => 9086220 [patent_doc_number] => 08557647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Method for fabricating field effect transistor devices with high-aspect ratio mask' [patent_app_type] => utility [patent_app_number] => 13/229154 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13229154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229154
Method for fabricating field effect transistor devices with high-aspect ratio mask Sep 8, 2011 Issued
Array ( [id] => 8859139 [patent_doc_number] => 08461676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Soldering relief method and semiconductor device employing same' [patent_app_type] => utility [patent_app_number] => 13/228925 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228925 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228925
Soldering relief method and semiconductor device employing same Sep 8, 2011 Issued
Array ( [id] => 8094955 [patent_doc_number] => 20120083077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/228433 [patent_app_country] => US [patent_app_date] => 2011-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20120083077.pdf [firstpage_image] =>[orig_patent_app_number] => 13228433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228433
Three dimensional semiconductor memory device and method of fabricating the same Sep 7, 2011 Issued
Array ( [id] => 8675410 [patent_doc_number] => 08383523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method for texturing silicon wafers, treatment liquid therefor, and use' [patent_app_type] => utility [patent_app_number] => 13/224821 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 894 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224821 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224821
Method for texturing silicon wafers, treatment liquid therefor, and use Sep 1, 2011 Issued
Array ( [id] => 8684471 [patent_doc_number] => 20130052755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'Automatically adjusting baking process for low-k dielectric material' [patent_app_type] => utility [patent_app_number] => 13/219317 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219317 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219317
Automatically adjusting baking process for low-k dielectric material Aug 25, 2011 Issued
Array ( [id] => 8659606 [patent_doc_number] => 20130040435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'METHOD FOR MANUFACTURING TRANSISTOR AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/377527 [patent_app_country] => US [patent_app_date] => 2011-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3602 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13377527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/377527
METHOD FOR MANUFACTURING TRANSISTOR AND SEMICONDUCTOR DEVICE Aug 8, 2011 Abandoned
Array ( [id] => 7500723 [patent_doc_number] => 20110263094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION' [patent_app_type] => utility [patent_app_number] => 13/176614 [patent_app_country] => US [patent_app_date] => 2011-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4226 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263094.pdf [firstpage_image] =>[orig_patent_app_number] => 13176614 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/176614
Method of forming finned semiconductor devices with trench isolation Jul 4, 2011 Issued
Array ( [id] => 8563753 [patent_doc_number] => 20120326324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/166679 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166679
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF Jun 21, 2011 Abandoned
Array ( [id] => 7486242 [patent_doc_number] => 20110250764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Method of thermally treating silicon with oxygen' [patent_app_type] => utility [patent_app_number] => 13/165502 [patent_app_country] => US [patent_app_date] => 2011-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5685 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250764.pdf [firstpage_image] =>[orig_patent_app_number] => 13165502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/165502
Method of thermally treating silicon with oxygen Jun 20, 2011 Issued
Array ( [id] => 8571645 [patent_doc_number] => 08338290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/163189 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5896 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163189
Method for fabricating semiconductor device Jun 16, 2011 Issued
Array ( [id] => 7711219 [patent_doc_number] => 20120003797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/159804 [patent_app_country] => US [patent_app_date] => 2011-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10363 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13159804 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/159804
Semiconductor device and manufacturing method thereof Jun 13, 2011 Issued
Array ( [id] => 8509780 [patent_doc_number] => 20120309188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'METHOD TO IMPROVE ADHESION FOR A SILVER FILLED OXIDE VIA FOR A NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/149653 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3822 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/149653
METHOD TO IMPROVE ADHESION FOR A SILVER FILLED OXIDE VIA FOR A NON-VOLATILE MEMORY DEVICE May 30, 2011 Abandoned
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