
Evren Seven
Examiner (ID: 608, Phone: (571)270-5666 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1114 |
| Issued Applications | 823 |
| Pending Applications | 121 |
| Abandoned Applications | 202 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7815217
[patent_doc_number] => 20120061837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/230106
[patent_app_country] => US
[patent_app_date] => 2011-09-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0061/20120061837.pdf
[firstpage_image] =>[orig_patent_app_number] => 13230106
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/230106 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | Sep 11, 2011 | Abandoned |
Array
(
[id] => 8846133
[patent_doc_number] => 08455312
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-04
[patent_title] => 'Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits'
[patent_app_type] => utility
[patent_app_number] => 13/199816
[patent_app_country] => US
[patent_app_date] => 2011-09-12
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13199816
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/199816 | Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits | Sep 11, 2011 | Issued |
Array
(
[id] => 8042443
[patent_doc_number] => 20120070957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-22
[patent_title] => 'AIR GAP FORMATION'
[patent_app_type] => utility
[patent_app_number] => 13/229673
[patent_app_country] => US
[patent_app_date] => 2011-09-10
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/229673 | Air gap formation | Sep 9, 2011 | Issued |
Array
(
[id] => 8172678
[patent_doc_number] => 20120108035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'Method of Fabricating Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 13/228966
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 13228966
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228966 | Method of Fabricating Semiconductor Device | Sep 8, 2011 | Abandoned |
Array
(
[id] => 7818068
[patent_doc_number] => 20120064688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 13/229570
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/229570 | METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR | Sep 8, 2011 | Abandoned |
Array
(
[id] => 8846113
[patent_doc_number] => 08455292
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-04
[patent_title] => 'Deposition of germanium film'
[patent_app_type] => utility
[patent_app_number] => 13/229440
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/229440 | Deposition of germanium film | Sep 8, 2011 | Issued |
Array
(
[id] => 7818060
[patent_doc_number] => 20120064680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/228867
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => publications/A1/0064/20120064680.pdf
[firstpage_image] =>[orig_patent_app_number] => 13228867
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228867 | METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME | Sep 8, 2011 | Abandoned |
Array
(
[id] => 7818051
[patent_doc_number] => 20120064671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'METHOD FOR PRODUCING CHIP ELEMENTS EQUIPPED WITH WIRE INSERTION GROOVES'
[patent_app_type] => utility
[patent_app_number] => 13/229021
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0064/20120064671.pdf
[firstpage_image] =>[orig_patent_app_number] => 13229021
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/229021 | Method for producing chip elements equipped with wire insertion grooves | Sep 8, 2011 | Issued |
Array
(
[id] => 9086220
[patent_doc_number] => 08557647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-15
[patent_title] => 'Method for fabricating field effect transistor devices with high-aspect ratio mask'
[patent_app_type] => utility
[patent_app_number] => 13/229154
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/229154 | Method for fabricating field effect transistor devices with high-aspect ratio mask | Sep 8, 2011 | Issued |
Array
(
[id] => 8859139
[patent_doc_number] => 08461676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-11
[patent_title] => 'Soldering relief method and semiconductor device employing same'
[patent_app_type] => utility
[patent_app_number] => 13/228925
[patent_app_country] => US
[patent_app_date] => 2011-09-09
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Array
(
[id] => 8094955
[patent_doc_number] => 20120083077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/228433
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228433 | Three dimensional semiconductor memory device and method of fabricating the same | Sep 7, 2011 | Issued |
Array
(
[id] => 8675410
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[patent_issue_date] => 2013-02-26
[patent_title] => 'Method for texturing silicon wafers, treatment liquid therefor, and use'
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Array
(
[id] => 8684471
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[patent_title] => 'Automatically adjusting baking process for low-k dielectric material'
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Array
(
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Array
(
[id] => 7500723
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[patent_title] => 'METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/176614 | Method of forming finned semiconductor devices with trench isolation | Jul 4, 2011 | Issued |
Array
(
[id] => 8563753
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[patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF'
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Array
(
[id] => 7486242
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[patent_title] => 'Method of thermally treating silicon with oxygen'
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Array
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Array
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Array
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