Search

Fahd A. Obeid

Supervisory Patent Examiner (ID: 4038, Phone: (571)270-3324 , Office: P/3687 )

Most Active Art Unit
3627
Art Unit(s)
4122, 3627, 4182, 3687
Total Applications
268
Issued Applications
79
Pending Applications
11
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19484359 [patent_doc_number] => 20240332401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => METHOD OF FORMING A NANO-FET SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/742017 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742017 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742017
METHOD OF FORMING A NANO-FET SEMICONDUCTOR DEVICE Jun 12, 2024 Pending
Array ( [id] => 19206240 [patent_doc_number] => 20240178139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => APPARATUS AND METHODS FOR GENERATING A CIRCUIT WITH HIGH DENSITY ROUTING LAYOUT [patent_app_type] => utility [patent_app_number] => 18/437130 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437130
Methods for generating a circuit with high density routing layout Feb 7, 2024 Issued
Array ( [id] => 19775356 [patent_doc_number] => 20250056782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/447544 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447544
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Aug 9, 2023 Pending
Array ( [id] => 19775356 [patent_doc_number] => 20250056782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/447544 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447544
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Aug 9, 2023 Pending
Array ( [id] => 18812991 [patent_doc_number] => 20230387328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/446918 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446918
SEMICONDUCTOR DEVICE AND METHOD Aug 8, 2023 Pending
Array ( [id] => 20189822 [patent_doc_number] => 12400947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Variable graduated capacitor structure and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/359950 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359950
Variable graduated capacitor structure and methods for forming the same Jul 26, 2023 Issued
Array ( [id] => 18776555 [patent_doc_number] => 20230371397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => BOTTOM ELECTRODE VIA AND CONDUCTIVE BARRIER DESIGN TO ELIMINATE ELECTRICAL SHORT IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/359289 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359289
Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices Jul 25, 2023 Issued
Array ( [id] => 19733867 [patent_doc_number] => 12211869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Optical blocking structures for black level correction pixels in an image sensor [patent_app_type] => utility [patent_app_number] => 18/358206 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 12717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358206 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358206
Optical blocking structures for black level correction pixels in an image sensor Jul 24, 2023 Issued
Array ( [id] => 19253095 [patent_doc_number] => 20240204092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/321284 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321284
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME May 21, 2023 Pending
Array ( [id] => 19054998 [patent_doc_number] => 20240096967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/177318 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177318
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Mar 1, 2023 Pending
Array ( [id] => 19054998 [patent_doc_number] => 20240096967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/177318 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177318
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Mar 1, 2023 Pending
Array ( [id] => 19054998 [patent_doc_number] => 20240096967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/177318 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177318
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Mar 1, 2023 Pending
Array ( [id] => 18473305 [patent_doc_number] => 20230207593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MULTILAYER SUBSTRATE AND IMAGE SENSOR UNIT [patent_app_type] => utility [patent_app_number] => 18/170639 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170639 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170639
MULTILAYER SUBSTRATE AND IMAGE SENSOR UNIT Feb 16, 2023 Pending
Array ( [id] => 18906130 [patent_doc_number] => 20240021615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/163573 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163573 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163573
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Feb 1, 2023 Pending
Array ( [id] => 19101148 [patent_doc_number] => 20240120376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => TRANSITION BETWEEN DIFFERENT ACTIVE REGIONS [patent_app_type] => utility [patent_app_number] => 18/159989 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159989 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/159989
TRANSITION BETWEEN DIFFERENT ACTIVE REGIONS Jan 25, 2023 Pending
Array ( [id] => 19191428 [patent_doc_number] => 20240170341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/152390 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152390
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE Jan 9, 2023 Pending
Array ( [id] => 18396752 [patent_doc_number] => 20230164973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/152202 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152202
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Jan 9, 2023 Pending
Array ( [id] => 18396752 [patent_doc_number] => 20230164973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/152202 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152202
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Jan 9, 2023 Pending
Array ( [id] => 18394977 [patent_doc_number] => 20230163198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => NANO-FET SEMICONDUCTOR DEVICE AND METHOD OF FORMING [patent_app_type] => utility [patent_app_number] => 18/151761 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151761 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151761
NANO-FET SEMICONDUCTOR DEVICE AND METHOD OF FORMING Jan 8, 2023 Pending
Array ( [id] => 18883194 [patent_doc_number] => 20240006563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD OF TRANSFERRING MICRO SEMICONDUCTOR CHIPS [patent_app_type] => utility [patent_app_number] => 18/084186 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084186
METHOD OF TRANSFERRING MICRO SEMICONDUCTOR CHIPS Dec 18, 2022 Pending
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