Search

Faisal M. Zaman

Examiner (ID: 4014, Phone: (571)272-6495 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2111, 2175, 2186, 2185, 2112
Total Applications
1096
Issued Applications
691
Pending Applications
85
Abandoned Applications
334

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15953023 [patent_doc_number] => 10664419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => I/O driven data transfer in a data processing network [patent_app_type] => utility [patent_app_number] => 15/881937 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881937
I/O driven data transfer in a data processing network Jan 28, 2018 Issued
Array ( [id] => 15198139 [patent_doc_number] => 10496564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Bus control circuit, information processing apparatus, and control method for bus control circuit [patent_app_type] => utility [patent_app_number] => 15/880044 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880044 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880044
Bus control circuit, information processing apparatus, and control method for bus control circuit Jan 24, 2018 Issued
Array ( [id] => 16178754 [patent_doc_number] => 20200225722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => POWER MANAGEMENT OF DISCRETE COMMUNICATION PORT COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/648206 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16648206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/648206
Power management of discrete communication port components Jan 24, 2018 Issued
Array ( [id] => 14628693 [patent_doc_number] => 20190227714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => COMMAND PROCESSING FOR A STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 15/879054 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879054 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879054
Command processing for a storage system Jan 23, 2018 Issued
Array ( [id] => 14629179 [patent_doc_number] => 20190227957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => METHOD FOR USING DEALLOCATED MEMORY FOR CACHING IN AN I/O FILTERING FRAMEWORK [patent_app_type] => utility [patent_app_number] => 15/879389 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879389
METHOD FOR USING DEALLOCATED MEMORY FOR CACHING IN AN I/O FILTERING FRAMEWORK Jan 23, 2018 Abandoned
Array ( [id] => 13807039 [patent_doc_number] => 10180786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-15 [patent_title] => Control circuit programming levels of pins and operating system utilizing the same [patent_app_type] => utility [patent_app_number] => 15/870892 [patent_app_country] => US [patent_app_date] => 2018-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870892
Control circuit programming levels of pins and operating system utilizing the same Jan 12, 2018 Issued
Array ( [id] => 13449213 [patent_doc_number] => 20180276149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => COMMON DIE IMPLEMENTATION FOR MEMORY DEVICES WITH INDEPENDENT INTERFACE PATHS [patent_app_type] => utility [patent_app_number] => 15/868775 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868775 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868775
COMMON DIE IMPLEMENTATION FOR MEMORY DEVICES WITH INDEPENDENT INTERFACE PATHS Jan 10, 2018 Abandoned
Array ( [id] => 14287141 [patent_doc_number] => 20190140855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SYSTEM AND METHOD FOR EFFICIENTLY DEVELOPING AND TESTING HOME AUTOMATION SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/860956 [patent_app_country] => US [patent_app_date] => 2018-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/860956
System and method for efficiently developing and testing home automation systems Jan 2, 2018 Issued
Array ( [id] => 14539295 [patent_doc_number] => 20190205269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => APPARATUS, METHODS, AND SYSTEMS FOR MULTICAST IN A CONFIGURABLE SPATIAL ACCELERATOR [patent_app_type] => utility [patent_app_number] => 15/859473 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 90912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859473
Apparatus, methods, and systems for multicast in a configurable spatial accelerator Dec 29, 2017 Issued
Array ( [id] => 16706413 [patent_doc_number] => 10956346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Storage system having an in-line hardware accelerator [patent_app_type] => utility [patent_app_number] => 15/857756 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 29517 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857756 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857756
Storage system having an in-line hardware accelerator Dec 28, 2017 Issued
Array ( [id] => 16063843 [patent_doc_number] => 10690863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Communication cable identification [patent_app_type] => utility [patent_app_number] => 15/840771 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840771
Communication cable identification Dec 12, 2017 Issued
Array ( [id] => 13240701 [patent_doc_number] => 10133549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Systems and methods for implementing a synchronous FIFO with registered outputs [patent_app_type] => utility [patent_app_number] => 15/831053 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831053 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831053
Systems and methods for implementing a synchronous FIFO with registered outputs Dec 3, 2017 Issued
Array ( [id] => 14047559 [patent_doc_number] => 20190079886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => HETEROGENEOUS ACCELERATOR FOR HIGHLY EFFICIENT LEARNING SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/825047 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825047
Heterogeneous accelerator for highly efficient learning systems Nov 27, 2017 Issued
Array ( [id] => 16494465 [patent_doc_number] => 10860507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Electronic systems having serial system bus interfaces and direct memory access controllers and methods of operating the same [patent_app_type] => utility [patent_app_number] => 15/822825 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822825
Electronic systems having serial system bus interfaces and direct memory access controllers and methods of operating the same Nov 26, 2017 Issued
Array ( [id] => 16046185 [patent_doc_number] => 10684965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Method to reduce write responses to improve bandwidth and efficiency [patent_app_type] => utility [patent_app_number] => 15/807151 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807151
Method to reduce write responses to improve bandwidth and efficiency Nov 7, 2017 Issued
Array ( [id] => 16299569 [patent_doc_number] => 20200285292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => POWER ADAPTERS FOR COMPONENT INTERCONNECT PORTS [patent_app_type] => utility [patent_app_number] => 16/756153 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16756153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/756153
POWER ADAPTERS FOR COMPONENT INTERCONNECT PORTS Nov 5, 2017 Abandoned
Array ( [id] => 12892063 [patent_doc_number] => 20180189196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => COMMUNICATION METHOD AND MOBILE TERMINAL [patent_app_type] => utility [patent_app_number] => 15/802057 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802057 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802057
Communication method and mobile terminal Nov 1, 2017 Issued
Array ( [id] => 14235369 [patent_doc_number] => 20190129857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => I/O DRIVEN DATA ROUTING AND CACHE ALLOCATION [patent_app_type] => utility [patent_app_number] => 15/801995 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801995
I/O driven data routing and cache allocation Nov 1, 2017 Issued
Array ( [id] => 15284725 [patent_doc_number] => 10515027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Storage device sharing through queue transfer [patent_app_type] => utility [patent_app_number] => 15/793899 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793899
Storage device sharing through queue transfer Oct 24, 2017 Issued
Array ( [id] => 14218751 [patent_doc_number] => 20190121760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => MANAGING EFFICIENT SELECTION OF A PARTICULAR PROCESSOR THREAD FOR HANDLING AN INTERRUPT [patent_app_type] => utility [patent_app_number] => 15/792755 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792755
Managing efficient selection of a particular processor thread for handling an interrupt Oct 24, 2017 Issued
Menu