Search

Faisal M. Zaman

Examiner (ID: 4014, Phone: (571)272-6495 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2111, 2175, 2186, 2185, 2112
Total Applications
1096
Issued Applications
691
Pending Applications
85
Abandoned Applications
334

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19375313 [patent_doc_number] => 12066878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Adaptive host bus power control [patent_app_type] => utility [patent_app_number] => 17/826532 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 19823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826532
Adaptive host bus power control May 26, 2022 Issued
Array ( [id] => 18826537 [patent_doc_number] => 11841813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => System and method for efficient communication bus arbitration [patent_app_type] => utility [patent_app_number] => 17/736525 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3363 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736525
System and method for efficient communication bus arbitration May 3, 2022 Issued
Array ( [id] => 19355638 [patent_doc_number] => 12056080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => High speed data transmission in battery management systems with isolated SPI interface [patent_app_type] => utility [patent_app_number] => 17/732114 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10822 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732114
High speed data transmission in battery management systems with isolated SPI interface Apr 27, 2022 Issued
Array ( [id] => 19314973 [patent_doc_number] => 12040804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Methods and systems for controlling frequency variation for a PLL reference clock [patent_app_type] => utility [patent_app_number] => 17/732307 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 12553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732307
Methods and systems for controlling frequency variation for a PLL reference clock Apr 27, 2022 Issued
Array ( [id] => 18730134 [patent_doc_number] => 20230344432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => ASYMMETRICAL CLOCK SEPARATION AND STAGE DELAY OPTIMIZATION IN SINGLE FLUX QUANTUM LOGIC [patent_app_type] => utility [patent_app_number] => 17/729614 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729614
Asymmetrical clock separation and stage delay optimization in single flux quantum logic Apr 25, 2022 Issued
Array ( [id] => 18728026 [patent_doc_number] => 20230342319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SMART NETWORK INTERFACE CONTROLLER OPERATING SYSTEM BINDING [patent_app_type] => utility [patent_app_number] => 17/730076 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730076
Smart network interface controller operating system binding Apr 25, 2022 Issued
Array ( [id] => 18147252 [patent_doc_number] => 20230021109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => DP-OUT ADAPTER AND ASSOCIATED CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/719406 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719406
DP-out adapter and associated control method Apr 12, 2022 Issued
Array ( [id] => 17751591 [patent_doc_number] => 20220229796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => DIRECT MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 17/716481 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716481
Direct memory access Apr 7, 2022 Issued
Array ( [id] => 20174799 [patent_doc_number] => 12393546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Communication with serial periphal interface information [patent_app_type] => utility [patent_app_number] => 18/547646 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10314 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18547646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/547646
Communication with serial periphal interface information Apr 5, 2022 Issued
Array ( [id] => 18677836 [patent_doc_number] => 20230315483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => PROCESSOR CORE SUBSYSTEM WITH OPEN-STANDARD NETWORK-ON-CHIP PORTS [patent_app_type] => utility [patent_app_number] => 17/712106 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712106
PROCESSOR CORE SUBSYSTEM WITH OPEN-STANDARD NETWORK-ON-CHIP PORTS Apr 1, 2022 Abandoned
Array ( [id] => 17738880 [patent_doc_number] => 20220224342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => CLOCKING ARCHITECTURE FOR A MULTI-DIE PACKAGE [patent_app_type] => utility [patent_app_number] => 17/711784 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711784
CLOCKING ARCHITECTURE FOR A MULTI-DIE PACKAGE Mar 31, 2022 Pending
Array ( [id] => 20009551 [patent_doc_number] => 20250147773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => ARITHMETIC APPARATUS AND PROGRAM OPERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/283631 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18283631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/283631
ARITHMETIC APPARATUS AND PROGRAM OPERATING METHOD Mar 29, 2022 Pending
Array ( [id] => 18659986 [patent_doc_number] => 20230305993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => CHIPLET ARCHITECTURE CHUNKING FOR UNIFORMITY ACROSS MULTIPLE CHIPLET CONFIGURATIONS [patent_app_type] => utility [patent_app_number] => 17/702235 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702235
CHIPLET ARCHITECTURE CHUNKING FOR UNIFORMITY ACROSS MULTIPLE CHIPLET CONFIGURATIONS Mar 22, 2022 Pending
Array ( [id] => 19159656 [patent_doc_number] => 20240152363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => MANAGEMENT DEVICE, COMMUNICATION SYSTEM, MANAGEMENT METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/281408 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18281408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/281408
MANAGEMENT DEVICE, COMMUNICATION SYSTEM, MANAGEMENT METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM Mar 13, 2022 Pending
Array ( [id] => 19087051 [patent_doc_number] => 20240113852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => WIRELESS COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/264683 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18264683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/264683
Wireless communication system Feb 9, 2022 Issued
Array ( [id] => 17613564 [patent_doc_number] => 20220155844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SYSTEM AND METHOD TO MAINTAIN OPTIMAL SYSTEM PERFORMANCE WITHIN USER DEFINED SYSTEM LEVEL POWER CAP IN A CHANGING WORKLOAD ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/587060 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587060
System and method to maintain optimal system performance within user defined system level power cap in a changing workload environment Jan 27, 2022 Issued
Array ( [id] => 17581277 [patent_doc_number] => 20220138132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => HETEROGENEOUS ACCELERATOR FOR HIGHLY EFFICIENT LEARNING SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/577370 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577370
Heterogeneous accelerator for highly efficient learning systems Jan 16, 2022 Issued
Array ( [id] => 18438283 [patent_doc_number] => 20230185578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => BIOS Personalities [patent_app_type] => utility [patent_app_number] => 17/549719 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549719
BIOS Personalities Dec 12, 2021 Abandoned
Array ( [id] => 18438847 [patent_doc_number] => 20230186142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => TECHNOLOGIES FOR HIGH-SPEED INTERFACES FOR CRYOGENIC QUANTUM CONTROL [patent_app_type] => utility [patent_app_number] => 17/549154 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549154
TECHNOLOGIES FOR HIGH-SPEED INTERFACES FOR CRYOGENIC QUANTUM CONTROL Dec 12, 2021 Abandoned
Array ( [id] => 18803359 [patent_doc_number] => 11836518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Processor graph execution using interrupt conservation [patent_app_type] => utility [patent_app_number] => 17/548463 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14080 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548463
Processor graph execution using interrupt conservation Dec 9, 2021 Issued
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