Fan S. Tsang

Array ( [id] => 6524406 [patent_doc_number] => 20100231261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Apparatus and Method for Mixed Single-Rail and Dual-Rail Combinational Logic with Completion Detection' [patent_app_type] => utility [patent_app_number] => 12/402265 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5004 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20100231261.pdf [firstpage_image] =>[orig_patent_app_number] => 12402265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8297461 [patent_doc_number] => 08225261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Methods for defining contact grid in dynamic array architecture' [patent_app_type] => utility [patent_app_number] => 12/399948 [patent_app_country] => US [patent_app_date] => 2009-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8606 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12399948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4441447 [patent_doc_number] => 07971163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Property generating apparatus, property generating method and program' [patent_app_type] => utility [patent_app_number] => 12/391752 [patent_app_country] => US [patent_app_date] => 2009-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971163.pdf [firstpage_image] =>[orig_patent_app_number] => 12391752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 128315 [patent_doc_number] => 07707531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus' [patent_app_type] => utility [patent_app_number] => 12/379361 [patent_app_country] => US [patent_app_date] => 2009-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707531.pdf [firstpage_image] =>[orig_patent_app_number] => 12379361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7780256 [patent_doc_number] => 08122404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits' [patent_app_type] => utility [patent_app_number] => 12/388932 [patent_app_country] => US [patent_app_date] => 2009-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5009 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122404.pdf [firstpage_image] =>[orig_patent_app_number] => 12388932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4606448 [patent_doc_number] => 07987434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Calculation system for inverse masks' [patent_app_type] => utility [patent_app_number] => 12/359174 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 72 [patent_no_of_words] => 18978 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987434.pdf [firstpage_image] =>[orig_patent_app_number] => 12359174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8366778 [patent_doc_number] => 08255857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Routing methods for integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/347871 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5968 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12347871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5332894 [patent_doc_number] => 20090113371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/347832 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5419 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113371.pdf [firstpage_image] =>[orig_patent_app_number] => 12347832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5332895 [patent_doc_number] => 20090113372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'INTERCONNECT ROUTING METHODS OF INTEGRATED CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/347902 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113372.pdf [firstpage_image] =>[orig_patent_app_number] => 12347902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5577322 [patent_doc_number] => 20090144684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'CLOCK MODEL FOR FORMAL VERIFICATION OF A DIGITAL CIRCUIT DESCRIPTION' [patent_app_type] => utility [patent_app_number] => 12/343415 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4651 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144684.pdf [firstpage_image] =>[orig_patent_app_number] => 12343415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9103 [patent_doc_number] => 07818694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'IC layout optimization to improve yield' [patent_app_type] => utility [patent_app_number] => 12/342353 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818694.pdf [firstpage_image] =>[orig_patent_app_number] => 12342353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5547485 [patent_doc_number] => 20090157362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'MODEL MODIFICATION METHOD FOR A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/336212 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157362.pdf [firstpage_image] =>[orig_patent_app_number] => 12336212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4642103 [patent_doc_number] => 08020139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations' [patent_app_type] => utility [patent_app_number] => 12/331212 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020139.pdf [firstpage_image] =>[orig_patent_app_number] => 12331212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8343232 [patent_doc_number] => 08245165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-14 [patent_title] => 'Methods and apparatus for waveform based variational static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/331072 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 12979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12331072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8655575 [patent_doc_number] => 08375343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Methods and apparatus for waveform based variational static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/331172 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 13009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12331172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4443769 [patent_doc_number] => 07900171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit' [patent_app_type] => utility [patent_app_number] => 12/256334 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5164 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900171.pdf [firstpage_image] =>[orig_patent_app_number] => 12256334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5418268 [patent_doc_number] => 20090044155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'METHOD AND SYSTEM FOR DESIGNING AN ELECTRONIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/255819 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20090044155.pdf [firstpage_image] =>[orig_patent_app_number] => 12255819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 28603 [patent_doc_number] => 07797666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Systems and methods for mapping arbitrary logic functions into synchronous embedded memories' [patent_app_type] => utility [patent_app_number] => 12/244635 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 3466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797666.pdf [firstpage_image] =>[orig_patent_app_number] => 12244635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8331722 [patent_doc_number] => 08239798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-07 [patent_title] => 'Methods, systems, and apparatus for variation aware extracted timing models' [patent_app_type] => utility [patent_app_number] => 12/185072 [patent_app_country] => US [patent_app_date] => 2008-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 15243 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12185072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7726422 [patent_doc_number] => 08099702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Method and apparatus for proximate placement of sequential cells' [patent_app_type] => utility [patent_app_number] => 12/182442 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8794 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099702.pdf [firstpage_image] =>[orig_patent_app_number] => 12182442 [rel_patent_id] =>[rel_patent_doc_number] =>)