Search

Fan S. Tsang

Examiner (ID: 2513)

Most Active Art Unit
2601
Art Unit(s)
2748, 2787, 2601, 2614, 2653, 2746, 2645, 2694, 2742
Total Applications
476
Issued Applications
312
Pending Applications
53
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5363064 [patent_doc_number] => 20090037858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method For Automatic Maximization of Coverage in Constrained Stimulus Driven Simulation' [patent_app_type] => utility [patent_app_number] => 11/831673 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037858.pdf [firstpage_image] =>[orig_patent_app_number] => 11831673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831673
Method for automatic maximization of coverage in constrained stimulus driven simulation Jul 30, 2007 Issued
Array ( [id] => 241486 [patent_doc_number] => 07594212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Automatic pin placement for integrated circuits to aid circuit board design' [patent_app_type] => utility [patent_app_number] => 11/888162 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594212.pdf [firstpage_image] =>[orig_patent_app_number] => 11888162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888162
Automatic pin placement for integrated circuits to aid circuit board design Jul 30, 2007 Issued
Array ( [id] => 5363059 [patent_doc_number] => 20090037853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'ASYNCHRONOUS, MULTI-RAIL DIGITAL CIRCUIT WITH GATING AND GATED SUB-CIRCUITS AND METHOD FOR DESIGNING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/831942 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037853.pdf [firstpage_image] =>[orig_patent_app_number] => 11831942 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831942
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same Jul 30, 2007 Issued
Array ( [id] => 175702 [patent_doc_number] => 07661085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Method and system for performing global routing on an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/781692 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3640 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/661/07661085.pdf [firstpage_image] =>[orig_patent_app_number] => 11781692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781692
Method and system for performing global routing on an integrated circuit design Jul 22, 2007 Issued
Array ( [id] => 127057 [patent_doc_number] => 07712067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-04 [patent_title] => 'Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints' [patent_app_type] => utility [patent_app_number] => 11/879912 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11815 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/712/07712067.pdf [firstpage_image] =>[orig_patent_app_number] => 11879912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/879912
Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints Jul 18, 2007 Issued
Array ( [id] => 245217 [patent_doc_number] => 07590961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Integrated circuit with signal skew adjusting cell selected from cell library' [patent_app_type] => utility [patent_app_number] => 11/774022 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3167 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590961.pdf [firstpage_image] =>[orig_patent_app_number] => 11774022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774022
Integrated circuit with signal skew adjusting cell selected from cell library Jul 5, 2007 Issued
Array ( [id] => 198611 [patent_doc_number] => 07636909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-22 [patent_title] => 'Automatically generating multithreaded datapaths' [patent_app_type] => utility [patent_app_number] => 11/825372 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/636/07636909.pdf [firstpage_image] =>[orig_patent_app_number] => 11825372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/825372
Automatically generating multithreaded datapaths Jul 4, 2007 Issued
Array ( [id] => 163572 [patent_doc_number] => 07676778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Circuit design optimization of integrated circuit based clock gated memory elements' [patent_app_type] => utility [patent_app_number] => 11/773412 [patent_app_country] => US [patent_app_date] => 2007-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676778.pdf [firstpage_image] =>[orig_patent_app_number] => 11773412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773412
Circuit design optimization of integrated circuit based clock gated memory elements Jul 3, 2007 Issued
Array ( [id] => 158042 [patent_doc_number] => 07685547 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Method, system, and computer program product for generating automated assumption for compositional verification' [patent_app_type] => utility [patent_app_number] => 11/772792 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8393 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685547.pdf [firstpage_image] =>[orig_patent_app_number] => 11772792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772792
Method, system, and computer program product for generating automated assumption for compositional verification Jul 1, 2007 Issued
Array ( [id] => 180135 [patent_doc_number] => 07657851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Device, system, and method for correction of integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/771152 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657851.pdf [firstpage_image] =>[orig_patent_app_number] => 11771152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771152
Device, system, and method for correction of integrated circuit design Jun 28, 2007 Issued
Array ( [id] => 4911485 [patent_doc_number] => 20080022252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/819573 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 20956 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20080022252.pdf [firstpage_image] =>[orig_patent_app_number] => 11819573 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819573
Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit Jun 27, 2007 Issued
Array ( [id] => 108158 [patent_doc_number] => 07725858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Providing a moat capacitance' [patent_app_type] => utility [patent_app_number] => 11/823222 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1749 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725858.pdf [firstpage_image] =>[orig_patent_app_number] => 11823222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/823222
Providing a moat capacitance Jun 26, 2007 Issued
Array ( [id] => 4854686 [patent_doc_number] => 20080320430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Spare Gate Array Cell Distribution Analysis' [patent_app_type] => utility [patent_app_number] => 11/767542 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1315 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320430.pdf [firstpage_image] =>[orig_patent_app_number] => 11767542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767542
Spare gate array cell distribution analysis Jun 24, 2007 Issued
Array ( [id] => 171993 [patent_doc_number] => 07669161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Minimizing effects of interconnect variations in integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 11/767292 [patent_app_country] => US [patent_app_date] => 2007-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11696 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669161.pdf [firstpage_image] =>[orig_patent_app_number] => 11767292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767292
Minimizing effects of interconnect variations in integrated circuit designs Jun 21, 2007 Issued
Array ( [id] => 171998 [patent_doc_number] => 07669166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-23 [patent_title] => 'Generation of a specification of a processor of network packets' [patent_app_type] => utility [patent_app_number] => 11/818722 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669166.pdf [firstpage_image] =>[orig_patent_app_number] => 11818722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/818722
Generation of a specification of a processor of network packets Jun 13, 2007 Issued
Array ( [id] => 4761355 [patent_doc_number] => 20080313581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'INDEPENDENT MIGRATION OF HIERARCHICAL DESIGNS WITH METHODS OF FINDING AND FIXING OPENS DURING MIGRATION' [patent_app_type] => utility [patent_app_number] => 11/762832 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3107 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313581.pdf [firstpage_image] =>[orig_patent_app_number] => 11762832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762832
Independent migration of hierarchical designs with methods of finding and fixing opens during migration Jun 13, 2007 Issued
Array ( [id] => 198610 [patent_doc_number] => 07636908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-22 [patent_title] => 'Generation of a specification of a network packet processor' [patent_app_type] => utility [patent_app_number] => 11/818792 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/636/07636908.pdf [firstpage_image] =>[orig_patent_app_number] => 11818792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/818792
Generation of a specification of a network packet processor Jun 13, 2007 Issued
Array ( [id] => 5249039 [patent_doc_number] => 20070245273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'TASK CONCURRENCY MANAGEMENT DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 11/761275 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 19330 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245273.pdf [firstpage_image] =>[orig_patent_app_number] => 11761275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/761275
Task concurrency management design method Jun 10, 2007 Issued
Array ( [id] => 298039 [patent_doc_number] => 07543263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Automatic trace shaping method' [patent_app_type] => utility [patent_app_number] => 11/760975 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 9313 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543263.pdf [firstpage_image] =>[orig_patent_app_number] => 11760975 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760975
Automatic trace shaping method Jun 10, 2007 Issued
Array ( [id] => 302274 [patent_doc_number] => 07539968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints' [patent_app_type] => utility [patent_app_number] => 11/759332 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2769 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539968.pdf [firstpage_image] =>[orig_patent_app_number] => 11759332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/759332
Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints Jun 6, 2007 Issued
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