Search

Fang-xing Jiang

Examiner (ID: 581, Phone: (571)270-7548 , Office: P/2815 )

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
386
Issued Applications
221
Pending Applications
0
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10270207 [patent_doc_number] => 20150155204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF' [patent_app_type] => utility [patent_app_number] => 14/615922 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 4334 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14615922 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/615922
TSV substrate structure and the stacked assembly thereof Feb 5, 2015 Issued
Array ( [id] => 11483430 [patent_doc_number] => 09589986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Array substrate, display device and method for fabricating array substrate' [patent_app_type] => utility [patent_app_number] => 14/435512 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4682 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435512 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/435512
Array substrate, display device and method for fabricating array substrate Jan 20, 2015 Issued
Array ( [id] => 10984446 [patent_doc_number] => 20160181391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'DIODE STRUCTURES WITH CONTROLLED INJECTION EFFICIENCY FOR FAST SWITCHING' [patent_app_type] => utility [patent_app_number] => 14/573187 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573187 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/573187
Diode structures with controlled injection efficiency for fast switching Dec 16, 2014 Issued
Array ( [id] => 11483532 [patent_doc_number] => 09590092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Super junction field effect transistor with internal floating ring' [patent_app_type] => utility [patent_app_number] => 14/540934 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6446 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540934 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/540934
Super junction field effect transistor with internal floating ring Nov 12, 2014 Issued
Array ( [id] => 11524986 [patent_doc_number] => 09608403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Dual bond pad structure for photonics' [patent_app_type] => utility [patent_app_number] => 14/531291 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2959 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531291
Dual bond pad structure for photonics Nov 2, 2014 Issued
Array ( [id] => 11765290 [patent_doc_number] => 09373745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Luminous element' [patent_app_type] => utility [patent_app_number] => 14/509880 [patent_app_country] => US [patent_app_date] => 2014-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14509880 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/509880
Luminous element Oct 7, 2014 Issued
Array ( [id] => 10973824 [patent_doc_number] => 20140376859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'MULTI-LAYER PHOTOELECTRIC INTEGRATED CIRCUIT DEVICE WITH OVERLAPPING DEVICES' [patent_app_type] => utility [patent_app_number] => 14/483583 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7587 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483583
MULTI-LAYER PHOTOELECTRIC INTEGRATED CIRCUIT DEVICE WITH OVERLAPPING DEVICES Sep 10, 2014 Abandoned
Array ( [id] => 10964831 [patent_doc_number] => 20140367863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/468522 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7887 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/468522
SEMICONDUCTOR DEVICE Aug 25, 2014 Abandoned
Array ( [id] => 10512821 [patent_doc_number] => 09240401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Semiconductor device and method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/446522 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446522
Semiconductor device and method of manufacturing a semiconductor device Jul 29, 2014 Issued
Array ( [id] => 11201135 [patent_doc_number] => 09431356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Semiconductor device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 14/446557 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8920 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446557
Semiconductor device and method of forming the same Jul 29, 2014 Issued
Array ( [id] => 10952781 [patent_doc_number] => 20140355802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'LISTENING SYSTEM WITH AN IMPROVED FEEDBACK CANCELLATION SYSTEM, A METHOD AND USE' [patent_app_type] => utility [patent_app_number] => 14/315115 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9848 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14315115 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/315115
Listening system with an improved feedback cancellation system, a method and use Jun 24, 2014 Issued
Array ( [id] => 10350910 [patent_doc_number] => 20150235915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Substrate Design for Semiconductor Packages and Method of Forming Same' [patent_app_type] => utility [patent_app_number] => 14/304331 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 10549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14304331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/304331
Substrate design for semiconductor packages and method of forming same Jun 12, 2014 Issued
Array ( [id] => 10909480 [patent_doc_number] => 20140312496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/266433 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3858 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/266433
SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE Apr 29, 2014 Abandoned
Array ( [id] => 10336523 [patent_doc_number] => 20150221528 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2015-08-06 [patent_title] => 'PROCESS FOR IMPROVING PACKAGE WARPAGE AND CONNECTION RELIABILITY THROUGH USE OF A BACKSIDE MOLD CONFIGURATION (BSMC)' [patent_app_type] => utility [patent_app_number] => 14/255349 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255349 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255349
PROCESS FOR IMPROVING PACKAGE WARPAGE AND CONNECTION RELIABILITY THROUGH USE OF A BACKSIDE MOLD CONFIGURATION (BSMC) Apr 16, 2014 Abandoned
Array ( [id] => 10336523 [patent_doc_number] => 20150221528 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2015-08-06 [patent_title] => 'PROCESS FOR IMPROVING PACKAGE WARPAGE AND CONNECTION RELIABILITY THROUGH USE OF A BACKSIDE MOLD CONFIGURATION (BSMC)' [patent_app_type] => utility [patent_app_number] => 14/255349 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255349 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255349
PROCESS FOR IMPROVING PACKAGE WARPAGE AND CONNECTION RELIABILITY THROUGH USE OF A BACKSIDE MOLD CONFIGURATION (BSMC) Apr 16, 2014 Abandoned
Array ( [id] => 9639482 [patent_doc_number] => 20140217592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 14/251728 [patent_app_country] => US [patent_app_date] => 2014-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3358 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/251728
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME Apr 13, 2014 Abandoned
Array ( [id] => 9557913 [patent_doc_number] => 20140175625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/189304 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189304 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189304
SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE ELEMENT Feb 24, 2014 Abandoned
Array ( [id] => 10350988 [patent_doc_number] => 20150235993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Thermal Performance Structure for Semiconductor Packages and Method of Forming Same' [patent_app_type] => utility [patent_app_number] => 14/181367 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14181367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/181367
Thermal performance structure for semiconductor packages and method of forming same Feb 13, 2014 Issued
Array ( [id] => 11701768 [patent_doc_number] => 09691693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Carrier-less silicon interposer using photo patterned polymer as substrate' [patent_app_type] => utility [patent_app_number] => 14/096387 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 8024 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096387 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096387
Carrier-less silicon interposer using photo patterned polymer as substrate Dec 3, 2013 Issued
Array ( [id] => 10260002 [patent_doc_number] => 20150144999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'Structure and Method For FinFET Device With Buried Sige Oxide' [patent_app_type] => utility [patent_app_number] => 14/090072 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090072
Structure and method for FinFET device with buried sige oxide Nov 25, 2013 Issued
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