Search

Fariba Sirjani

Examiner (ID: 675, Phone: (571)270-1499 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2659, 2626
Total Applications
600
Issued Applications
434
Pending Applications
62
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17316974 [patent_doc_number] => 20210406023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => PARALLEL SLICE PROCESSOR HAVING A RECIRCULATING LOAD-STORE QUEUE FOR FAST DEALLOCATION OF ISSUE QUEUE ENTRIES [patent_app_type] => utility [patent_app_number] => 17/467882 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467882
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Sep 6, 2021 Issued
Array ( [id] => 17316962 [patent_doc_number] => 20210406011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Systems, Apparatuses, And Methods For Fused Multiply Add [patent_app_type] => utility [patent_app_number] => 17/468258 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468258
Systems, apparatuses, and methods for fused multiply add Sep 6, 2021 Issued
Array ( [id] => 18015073 [patent_doc_number] => 11507369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Systems, apparatuses, and methods for fused multiply add [patent_app_type] => utility [patent_app_number] => 17/465905 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 19620 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465905
Systems, apparatuses, and methods for fused multiply add Sep 2, 2021 Issued
Array ( [id] => 17955236 [patent_doc_number] => 11481343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Transporting request types with different latencies [patent_app_type] => utility [patent_app_number] => 17/459525 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 20402 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459525
Transporting request types with different latencies Aug 26, 2021 Issued
Array ( [id] => 18104111 [patent_doc_number] => 11543997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Memory system and method for controlling nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/406619 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 21902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406619
Memory system and method for controlling nonvolatile memory Aug 18, 2021 Issued
Array ( [id] => 18606813 [patent_doc_number] => 11748280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Broadcast scope selection in a data processing system utilizing a memory topology data structure [patent_app_type] => utility [patent_app_number] => 17/394117 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 12643 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/394117
Broadcast scope selection in a data processing system utilizing a memory topology data structure Aug 3, 2021 Issued
Array ( [id] => 18169917 [patent_doc_number] => 20230036528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => System and Method for Storage Tiering Optimization [patent_app_type] => utility [patent_app_number] => 17/390220 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390220
System and method for storage tiering optimization Jul 29, 2021 Issued
Array ( [id] => 17216382 [patent_doc_number] => 20210349720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AND ACCUMULATION [patent_app_type] => utility [patent_app_number] => 17/382917 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382917
Systems, methods, and apparatuses for tile matrix multiplication and accumulation Jul 21, 2021 Issued
Array ( [id] => 18982543 [patent_doc_number] => 11907721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Inserting predefined pad values into a stream of vectors [patent_app_type] => utility [patent_app_number] => 17/379528 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379528
Inserting predefined pad values into a stream of vectors Jul 18, 2021 Issued
Array ( [id] => 18234932 [patent_doc_number] => 11599491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => System on chip having semaphore function and method for implementing semaphore function [patent_app_type] => utility [patent_app_number] => 17/376590 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376590
System on chip having semaphore function and method for implementing semaphore function Jul 14, 2021 Issued
Array ( [id] => 18826532 [patent_doc_number] => 11841808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => System and method for processing requests in a multithreaded system [patent_app_type] => utility [patent_app_number] => 17/375499 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375499
System and method for processing requests in a multithreaded system Jul 13, 2021 Issued
Array ( [id] => 17187218 [patent_doc_number] => 20210334103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => NESTED LOOP CONTROL [patent_app_type] => utility [patent_app_number] => 17/367384 [patent_app_country] => US [patent_app_date] => 2021-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367384
Nested loop control Jul 3, 2021 Issued
Array ( [id] => 18330721 [patent_doc_number] => 11635963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Address manipulation using indices and tags [patent_app_type] => utility [patent_app_number] => 17/364718 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364718
Address manipulation using indices and tags Jun 29, 2021 Issued
Array ( [id] => 18095700 [patent_doc_number] => 20220414041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => HIGH BIT RATE COMMUNICATION INTERFACE WITH COMMON MODE VOLTAGE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/362060 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362060
High bit rate communication interface with common mode voltage adjustment Jun 28, 2021 Issued
Array ( [id] => 18095841 [patent_doc_number] => 20220414182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR MATRIX MULTIPLICATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/359519 [patent_app_country] => US [patent_app_date] => 2021-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359519
Apparatuses, methods, and systems for instructions for matrix multiplication instructions Jun 25, 2021 Issued
Array ( [id] => 19719362 [patent_doc_number] => 12204901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Cache support for indirect loads and indirect stores in graph applications [patent_app_type] => utility [patent_app_number] => 17/359305 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 15235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359305
Cache support for indirect loads and indirect stores in graph applications Jun 24, 2021 Issued
Array ( [id] => 18095510 [patent_doc_number] => 20220413851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => REGISTER FILE FOR SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 17/304794 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304794
Register file for systolic array Jun 24, 2021 Issued
Array ( [id] => 17143723 [patent_doc_number] => 20210311736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => VECTOR BIT TRANSPOSE [patent_app_type] => utility [patent_app_number] => 17/353908 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353908
Vector bit transpose Jun 21, 2021 Issued
Array ( [id] => 17337825 [patent_doc_number] => 20220004156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => INDUSTRIAL CONTROL SYSTEM HAVING MULTI-LAYERED CONTROL LOGIC EXECUTION [patent_app_type] => utility [patent_app_number] => 17/352779 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352779
Industrial control system having multi-layered control logic execution Jun 20, 2021 Issued
Array ( [id] => 17956149 [patent_doc_number] => 11482262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Per pin Vref for data receivers in non-volatile memory system [patent_app_type] => utility [patent_app_number] => 17/348904 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348904 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348904
Per pin Vref for data receivers in non-volatile memory system Jun 15, 2021 Issued
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